Metal Gate Stack Fabrication for Leakage Reduction
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Solution Overview
Problem
As MOS transistor feature sizes decrease, the high resistance of polysilicon gate electrodes limits the speed of semiconductor devices, necessitating the replacement with metal gate electrodes through the RMG process, but this introduces challenges in achieving optimal capacitance and operation characteristics.
Innovation Solution
A method for fabricating semiconductor devices involves forming interlayer insulating layers, high-k dielectric layers, diffusion layers, blocking layers, barrier layers, work function adjustment layers, and capping layers to improve the operation characteristics, including annealing to bond oxygen atoms and adjust the dielectric layers, thereby enhancing the performance of metal gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon gate electrode is used, then high temperature annealing can be performed and self-aligned source/drain structure can be formed, but the device operates at lower speed due to high resistance
Solution Approach 1:
The patent replaces the polysilicon gate electrode material with a metal gate electrode material, fundamentally changing the electrical parameters of the gate. This material substitution reduces gate resistance significantly, enabling higher operation speeds while maintaining compatibility with existing CMOS fabrication processes through the RMG approach
Solution Approach 2:
The patent uses an intermediate polysilicon gate structure during fabrication that is later replaced by metal. The polysilicon serves as a temporary placeholder that allows standard high-temperature processing to occur, then gets removed and replaced with the final metal gate structure, bridging the gap between existing processes and new material requirements
2Speed
If metal gate electrode is used to compensate for high resistance, then operation speed improves, but achieving optimal capacitance and operation characteristics becomes challenging
Solution Approach 1:
The patent employs a composite gate structure consisting of multiple layers including metal gate electrode, high-k dielectric layer, and work function adjustment layer. This composite approach allows independent optimization of different functions: the metal provides low resistance for speed, the high-k dielectric provides high capacitance for drive strength, and the work function layer tunes the electrical characteristics
Solution Approach 2:
The patent applies different materials and properties to different regions of the gate structure. The work function adjustment layer is selectively applied to tune threshold voltage characteristics in specific device regions, while the high-k dielectric is conformally deposited to ensure uniform capacitance distribution across the gate surface
3Length of moving object
If feature size is decreased, then device scaling is achieved, but capacitance between gate and channel decreases and operation characteristics deteriorate
Solution Approach 1:
The patent changes the dielectric constant parameter by introducing high-k dielectric materials (such as HfO2, ZrO2, or their alloys) in the gate stack. This increases the gate capacitance per unit area, compensating for the reduced gate area caused by smaller feature sizes and maintaining the drive current capability despite scaling
Solution Approach 2:
The patent moves from optimizing purely in the planar dimensions to utilizing the vertical dimension through multi-layer gate stacks. By stacking multiple functional layers (metal gate, high-k dielectric, work function layer) vertically, the patent achieves enhanced capacitance and controlled electrical characteristics without increasing the lateral footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly improves the operation characteristics of semiconductor devices by reducing leakage current and enhancing tunneling effects, resulting in improved performance compared to conventional methods.
Implementation Method 1
forming a high-k dielectric layer in the first trench
Implementation Method 2
subsequently performing annealing
Implementation Method 3
annealing to bond oxygen atoms
Implementation Method 4
enhancing tunneling effects
Data Source
AI summary
Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.