Metal Gate Stack Layout for Lower Gate Resistance
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Solution Overview
Problem
As transistor feature sizes decrease, the fraction of the gate stack volume occupied by the conductive metal gate electrode layer decreases, leading to increased gate resistance and reduced switching power.
Innovation Solution
The method involves forming a semiconductor channel and depositing source and drain electrodes, followed by the creation of dielectric spacers that define a gate void. A dielectric layer and a work-function metal layer are deposited on the bottom wall of the gate void, with the work-function metal layer etched away from the sidewalls, allowing for a higher volume of conductive metal gate material to be deposited within the gate void.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If transistor feature sizes are decreased, then switching power is reduced, but gate resistance increases due to decreased fraction of conductive metal gate electrode layer volume
Solution Approach 1:
The gate stack is segmented into distinct functional layers: a dielectric layer, a work-function metal layer, and a conductive metal gate electrode layer. This segmentation allows each layer to be optimized independently - the work-function layer controls electrical characteristics while the conductive metal layer maximizes volume for low resistance, resolving the contradiction between reduced feature size and maintained gate resistance performance.
Solution Approach 2:
Different regions of the gate stack are assigned different material properties and functions. The bottom portion contains the work-function metal layer for electrical control, while the upper and lateral portions are filled with conductive metal gate material to maximize volume and minimize resistance. This local differentiation allows simultaneous optimization of both switching power and gate resistance.
2Quantity of substance
If the fraction of gate stack volume occupied by conductive metal gate electrode layer is decreased, then gate resistance increases
Solution Approach 1:
The conductive metal gate material is extended into the lateral dimension by filling the gate void between the dielectric spacers, not just vertically above the channel. This three-dimensional filling approach maximizes the volume of conductive metal gate material, thereby reducing gate resistance while maintaining compatibility with scaled transistor dimensions.
Solution Approach 2:
The gate stack employs a composite structure combining dielectric material, work-function metal, and conductive metal gate material. This composite approach allows the work-function layer to be thin (minimizing its volume occupation) while the conductive metal layer occupies maximum volume, resolving the contradiction between layer thickness and conductive volume fraction.
3Ease of manufacture
If dielectric layer and work-function metal layer are deposited on sidewalls of gate void, then volume available for conductive metal gate material is reduced
Solution Approach 1:
The work-function metal layer is selectively removed from the sidewalls of the gate void through selective etching, leaving it only on the bottom wall. This extraction of the work-function layer from non-essential regions (sidewalls) eliminates the volume conflict, allowing the conductive metal gate material to fill the entire available space between the dielectric spacers, thereby maximizing its volume while maintaining the necessary work-function control at the channel interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the proportion of the gate stack volume filled with conductive metal gate material, reducing gate resistance and enhancing switching power efficiency.
Implementation Method 1
depositing a dielectric layer may be performed using a vapor deposition technique
Implementation Method 2
the etching may be performed using a combination of gas phase etching and wet etching
Data Source
AI summary
Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.