Metal Gate Stack Selective Etching for CMOS Resistance
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Solution Overview
Problem
Current CMOS technology faces challenges in reducing metal gate stack resistance, particularly in n-FET devices, due to increased complexity and limited gate materials, especially at the 14 nm node and beyond, leading to higher gate resistance and potential leakage issues in n-FET devices.
Innovation Solution
The use of a highly selective titanium-aluminum carbide to titanium nitride wet etch chemistry with a high etch ratio allows for the selective removal of the TiAlC layer in p-FET devices while retaining the TiN cap layer, forming an improved metal gate stack configuration that reduces n-FET gate resistance and enhances p-FET negative-bias temperature instability (NBTI) performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard metal gate stack is used in n-FET devices, then the device structure is simple and manufacturing is easier, but the gate resistance is high leading to performance degradation
Solution Approach 1:
The metal gate stack is segmented into multiple functional layers: a TiN cap layer for low resistance and a TiAlC layer for workfunction control. This segmentation allows each layer to optimize its specific function, reducing overall gate resistance while maintaining proper device operation.
Solution Approach 2:
The invention uses a composite metal gate stack combining TiN and TiAlC layers. The TiN cap layer provides low resistance pathways, while the TiAlC layer beneath controls the workfunction. This composite structure achieves both low resistance and proper electrical characteristics that single-material gates cannot provide.
2Reliability
If the TiAlC layer is removed in p-FET devices to correct workfunction differences, then NBTI performance improves, but additional selective etching process is required
Solution Approach 1:
The metal gate stack structure is made local quality by selectively removing the TiAlC layer only in p-FET devices while retaining it in n-FET devices. This local modification corrects workfunction differences specific to p-FETs and improves NBTI performance without affecting n-FET operation.
Solution Approach 2:
The invention changes the structural parameters of the metal gate stack by selectively removing the TiAlC layer in p-FET devices. This parameter change (presence or absence of TiAlC) adjusts the workfunction and electrical characteristics to optimize p-FET performance and reduce NBTI effects.
3Manufacturing precision
If a highly selective TiAlC to TiN etch chemistry is used, then selective removal of TiAlC from p-FET is achieved with high etch ratio, but process development and control become more challenging
Solution Approach 1:
The TiN cap layer acts as an intermediary protective layer during the selective etching process. It protects the underlying high-κ dielectric from damage while allowing selective removal of the TiAlC layer through the TiN using highly selective etch chemistry.
Solution Approach 2:
The composite TiN/TiAlC metal gate stack enables selective etching by providing materials with vastly different etch rates. The TiAlC layer etches much faster than TiN, allowing selective removal with high precision while the TiN layer remains intact to protect underlying structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces n-FET gate resistance by approximately 200-400 ohm/per square and improves p-FET reliability by correcting workfunction differences and reducing NBTI, leading to enhanced device performance.
Implementation Method 1
removing the TiAlC layer may include using a selective TiAlC to TiN wet etch chemistry solution with a substantially high TiAlC to TiN etch ratio
Implementation Method 2
etching the third metal layer may include using a first wet etch chemistry solution including hydrogen peroxide (H2O2)
Data Source
AI summary
A method includes forming an n-FET device and a p-FET device on a substrate, each of the n-FET device and the p-FET device include a metal gate stack consisting of a titanium-aluminum carbide (TiAlC) layer above and in direct contact with a titanium nitride (TiN) cap, and removing, from the p-FET device, the TiAlC layer selective to the TiN cap. The removal of the TiAlC layer includes using a selective TiAlC to TiN wet etch chemistry solution with a substantially high TiAlC to TiN etch ratio such that the TiN cap remains in the p-FET device.