Metal Gate Stack Structure for Low-Resistance FinFET and GAA Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity of fabrication processes as feature sizes decrease, making it difficult to maintain device performance and efficiency.
Innovation Solution
The formation of semiconductor device structures using FinFETs and GAA transistor structures with advanced patterning techniques such as double-patterning or multi-patterning processes, combined with the use of a silicon-containing layer and work function metal layers to improve transistor performance by reducing electrical resistance and enhancing threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then productivity and production efficiency are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming first and second trenches at different depths, selective epitaxial growth in specific regions, and staged doping processes. This segmentation allows each step to be optimized independently, managing overall process complexity while enabling continued scaling.
Solution Approach 2:
Different regions of the semiconductor structure are given different properties through selective epitaxial growth and targeted doping. The source/drain regions, channel regions, and isolation regions are treated differently with specific materials and processes applied only where needed, allowing complex device functionality to be achieved through localized modifications rather than global process changes.
2Productivity
If feature sizes decrease to increase functional density, then more devices per chip area are achieved, but manufacturing precision requirements become more difficult to meet
Solution Approach 1:
Shallow trench isolation structures and epitaxial regions are formed in advance before final device fabrication steps. The isolation regions are created at defined depths with controlled doping profiles before the main device structures are built, establishing precise geometric boundaries that guide subsequent processing steps and ensure consistent feature dimensions.
Solution Approach 2:
Traditional mechanical lithographic patterning is supplemented and replaced with self-aligned epitaxial growth and selective doping processes. The epitaxial regions grow conformally to underlying structures, automatically defining precise boundaries without requiring additional lithographic steps, thereby maintaining manufacturing precision at smaller feature sizes.
3Reliability
If advanced patterning techniques are used to form FinFET and GAA structures, then transistor performance is improved, but fabrication process complexity increases
Solution Approach 1:
The semiconductor structure employs nested isolation regions where a first shallow isolation region contains a second deeper isolation region, which in turn contains the active device structures. This nested arrangement allows multiple isolation functions to be achieved within a compact vertical footprint, enabling advanced device architectures without proportionally increasing lateral process complexity.
Solution Approach 2:
The patent transitions from planar device structures to three-dimensional FinFET and gate-all-around nanowire configurations. The epitaxial growth and doping processes are applied in the vertical dimension with precise depth control, allowing enhanced transistor performance through increased effective channel width and improved gate control without requiring proportional increases in lithographic resolution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of reliable semiconductor devices with improved performance and reduced electrical resistance, addressing the challenges of scaling down while maintaining efficiency and complexity control in fabrication processes.
Implementation Method 1
The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer includes an oxide material.