Metal Gate Stacks for Flash Memory Programming Speed
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Solution Overview
Problem
Current flash memory technologies face challenges in achieving faster programming speeds and improved capacitive coupling in memory cells, particularly with the scaling of feature sizes in semiconductor integrated circuits, which affects the efficiency of read and write operations.
Innovation Solution
The implementation of metal gate stacks for erase and control gates in flash memory cells, which enhances capacitive coupling and allows for faster programming speeds by using potentials at both the erase and control gates, while also simplifying the manufacturing process by aligning gate heights through CMP processes and incorporating high-κ dielectric layers to improve thermal budget and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If polysilicon gate electrode is used in flash memory cells, then manufacturing process is simpler, but programming speed is slower and capacitive coupling is reduced
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, cobalt, or copper), which fundamentally alters the electrical properties including conductivity and capacitive coupling characteristics. This material substitution enables faster programming speeds while maintaining compatibility with existing semiconductor manufacturing processes through established metal deposition techniques.
Solution Approach 2:
The patent employs composite gate electrode structures combining metal layers with dielectric materials (such as high-κ dielectrics like hafnium oxide or silicon oxide). This composite approach optimizes both electrical performance for fast programming and manufacturing feasibility, allowing the metal gate to provide superior capacitive coupling while the dielectric layers ensure process compatibility and electrical isolation.
2Quantity of substance
If feature size is decreased to increase functional density, then memory array density improves, but capacitive coupling in memory cells deteriorates
Solution Approach 1:
The patent changes the gate electrode material from polysilicon to metal, which fundamentally alters the electrical properties including conductivity and capacitive coupling characteristics. This material substitution enables faster programming speeds while maintaining compatibility with existing semiconductor manufacturing processes through established metal deposition techniques.
Solution Approach 2:
The patent employs composite gate electrode structures combining metal layers with dielectric materials (such as high-κ dielectrics like hafnium oxide or silicon oxide). This composite approach optimizes both electrical performance for fast programming and manufacturing feasibility, allowing the metal gate to provide superior capacitive coupling while the dielectric layers ensure process compatibility and electrical isolation.
3Duration of action of moving object
If conventional gate structures are used, then manufacturing process is established, but programming time is excessive (approximately 100 ms)
Solution Approach 1:
The patent changes the gate electrode material from polysilicon to metal, which fundamentally alters the electrical properties including conductivity and capacitive coupling characteristics. This material substitution enables faster programming speeds while maintaining compatibility with existing semiconductor manufacturing processes through established metal deposition techniques.
Solution Approach 2:
The patent incorporates metal gate electrode formation into the existing semiconductor manufacturing flow by performing metal deposition and patterning as preliminary steps before final device assembly. This approach allows the metal gate structure to be established early in the process, enabling subsequent steps to proceed efficiently and achieving fast programming speeds without adding significant manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution results in significantly reduced programming times, improved control gate coupling ratios, and reduced manufacturing complexity, with programming speeds decreased from approximately 100 ms to 20 ms, and enhanced electrical performance of memory devices.
Implementation Method 1
incorporating high-κ dielectric layers to improve thermal budget and electrical performance
Implementation Method 2
enhances capacitive coupling and allows for faster programming speeds by using potentials at both the erase and control gates
Data Source
AI summary
A memory device includes a substrate, a transistor, and a memory cell. The substrate includes a cell region and a logic region. The transistor is over the logic region and includes a first metal gate stack. The memory cell is over the cell region and includes an erase gate. The erase gate is a metal gate stack.