Multi-Layer Metal Gate Stress Engineering for Carrier Mobility
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Solution Overview
Problem
Conventional stress technologies for semiconductor devices become less effective as device sizes decrease, leading to reduced carrier mobility and increased gate current leakage due to the limitations of thin film stress layers and high-K dielectric materials, which struggle to regulate device thresholds effectively.
Innovation Solution
A semiconductor device with a multi-layer metal gate structure that applies opposite stresses to channel regions of MOSFETs, using high-stress gate filling layers and work function metal diffusion blocking layers to enhance carrier mobility and device performance, independent of device size, and incorporates high-K dielectric materials to improve gate insulating capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stress technologies (embedded SiGe source/drain, stress liner, spacer) are used to enhance carrier mobility, then device performance is improved at larger feature sizes, but effectiveness is significantly reduced at 45 nm and below due to thinning film requirements and increased dislocation/offset
Solution Approach 1:
The patent changes the stress application mechanism from indirect (through source/drain or spacer) to direct (through gate electrode) by selecting metal materials with different stress characteristics for the gate electrode, enabling effective stress application at 45 nm and below without requiring thick stress-inducing layers
Solution Approach 2:
The patent extracts the stress application function from the source/drain structure and spacer structure, concentrating it in the gate electrode structure, thereby simplifying the overall device structure and improving manufacturing precision at small feature sizes
2Object-affected harmful factors
If high-K dielectric materials are used to improve gate insulating capability and reduce leakage, then gate current leakage is reduced, but regulation of device thresholds becomes difficult due to interfacial charges and polarization charges
Solution Approach 1:
The patent uses a composite gate electrode structure combining metal nitride (for work function control) and metal (for stress application), enabling simultaneous threshold voltage regulation and stress-induced mobility enhancement while using high-K dielectric materials
Solution Approach 2:
The patent applies different material properties to different parts of the gate electrode structure: metal nitride for electrical property control and metal for mechanical stress control, thereby achieving both threshold regulation and leakage reduction
3Productivity
If device feature size is reduced to continue scaling, then integration density is improved, but conventional stress technologies become less effective and require higher stress precision with thinner films
Solution Approach 1:
The patent changes the stress application approach from requiring thick films to using thin gate electrode layers with controlled intrinsic stress, enabling effective stress application at 45 nm and below without compromising manufacturing precision
Solution Approach 2:
The patent replaces the mechanical stress induction method (using thick stress-inducing layers) with a material property-based method (using intrinsic stress of thin metal gate electrode layers), thereby maintaining effectiveness at small feature sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances carrier mobility and device performance by applying precise stresses to channel regions, improving carrier mobility and reducing gate current leakage, while allowing for better regulation of device thresholds through the use of high-K dielectric materials.
Implementation Method 1
the gate filling layer has a second stress, and the first stress is opposite to the second stress
Data Source
AI summary
The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.