Metal Gate Transistor Shrinkage Compensation via Sidewall Spacer Etching
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Solution Overview
Problem
Existing metal gate transistors face challenges due to high temperature processes that cause the gate dielectric and work function layers to shrink, leading to performance issues as the widths and lengths of these layers become smaller than the metal gate, affecting transistor performance.
Innovation Solution
A method involving the formation of a dielectric layer with sidewalls protruding from the dummy gate, using a sidewall spacer as an etching mask to create a gate dielectric layer that compensates for shrinkage, ensuring the metal gate's dimensions remain compatible with the dielectric and work function layers, thereby maintaining optimal transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature processes (ion implantation and rapid thermal annealing at temperatures greater than 300°C) are used to fabricate the metal gate transistor, then the doping and activation processes can be effectively performed, but the gate dielectric layer and work function layer shrink, causing their widths and lengths to become smaller than the dummy gate, which affects transistor performance
Solution Approach 1:
The patent forms the gate dielectric layer and work function layer with dimensions larger than the dummy gate before the high temperature processes. This preliminary oversizing compensates for the expected shrinkage that will occur during subsequent ion implantation and rapid thermal annealing processes, ensuring that the final dimensions after shrinkage still match the metal gate dimensions.
Solution Approach 2:
The patent intentionally creates an opposite effect to counteract the harmful shrinkage. By making the gate dielectric layer and work function layer wider and longer than the dummy gate initially, the design anticipates and counteracts the shrinkage that will occur during high temperature processing, thereby maintaining dimensional compatibility with the metal gate after processing.
2Ease of manufacture
If the gate dielectric layer and work function layer are formed with the same width as the dummy gate, then the initial fabrication is simplified, but after high temperature processes the layers shrink and become narrower than the metal gate, requiring complex etching process control to compensate
Solution Approach 1:
Instead of forming the gate dielectric layer and work function layer with dimensions exactly matching the dummy gate, the patent preliminarily forms them with larger dimensions. This preliminary action simplifies the fabrication by avoiding complex real-time compensation adjustments, while still achieving the desired final dimensional match after accounting for predictable shrinkage.
3Manufacturing precision
If complex etching process control is implemented to make gate dielectric layer and work function layer sidewalls protrude from the dummy gate sidewalls, then shrinkage compensation can be achieved, but the device complexity and process difficulty increase significantly
Solution Approach 1:
The patent performs the shrinkage compensation in advance during the formation of the gate dielectric layer and work function layer, rather than attempting complex real-time adjustments during etching. By preliminarily establishing larger dimensions, the need for complex etching process control is eliminated, reducing device complexity while achieving the same shrinkage compensation effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the metal gate from becoming wider or longer than the dielectric and work function layers, even after high temperature processes, thus enhancing transistor performance by maintaining structural compatibility and reducing the complexity of controlling etching processes.
Implementation Method 1
using a sidewall spacer as an etching mask to create a gate dielectric layer that compensates for shrinkage
Implementation Method 2
The high temperature processes may cause the gate dielectric layer 2 and the work function layer 3 to shrink
Data Source
AI summary
A method is provided for fabricating a metal gate transistor. The method includes providing a semiconductor substrate; and forming a dielectric layer on the semiconductor substrate. The method also includes forming at least one dummy gate on the dielectric layer; and forming a first sidewall spacer around the dummy gate. Further, the method includes forming a gate dielectric layer with sidewalls protruding from sidewalls of the dummy gate and vertical to the semiconductor substrate by etching the dielectric layer using the first sidewall spacer and the dummy gate as an etching mask; and removing the dummy gate to form a trench. Further, the method also includes forming a metal gate in the trench; and forming a source region and a drain region in the semiconductor substrate.