Metal Gate Trench Reshaping for Seam-Free Gap Filling
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Solution Overview
Problem
The formation of metal gates in semiconductor integrated circuits faces challenges with voids or seams being trapped in high aspect ratio gate trenches, leading to punch-through defects and poor growth of gate metal caps, particularly in sub-10 nm technology nodes.
Innovation Solution
A gradient passivation process is applied to transform the re-entrant profile of the gate trench into a U-shape or V-shape, followed by a selective etch to enlarge openings, facilitating seamless gap-filling and improving the uniformity and integrity of gate metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a metal gate gap-filling process is used to deposit metal layers in a gate trench, then the metal gate structure is formed, but voids or seams are trapped in the high aspect ratio gate trench
Solution Approach 1:
A mandrel structure is formed at the bottom of the gate trench before depositing the metal gate electrode layers. This preliminary structure serves as a foundation that prevents void formation during subsequent metal layer deposition, ensuring complete filling of the high aspect ratio gate trench without seams or voids.
Solution Approach 2:
The mandrel acts as an intermediary structure between the gate trench bottom and the metal gate electrode layers. It provides a stable base that facilitates uniform metal layer deposition and prevents direct contact issues between the metal layers and the trench bottom, thereby eliminating void formation.
2Productivity
If the gate trench has a high aspect ratio to accommodate scaled down features, then transistor density increases, but voids are more easily trapped during metal deposition
Solution Approach 1:
The mandrel structure is formed in advance at the bottom of the high aspect ratio gate trench, providing a foundation that enables uniform metal layer deposition even in the challenging geometry, thus maintaining manufacturing precision while achieving high transistor density.
Solution Approach 2:
The mandrel provides localized structural support at the critical bottom region of the gate trench, where void formation is most likely to occur. This local intervention ensures uniform metal filling in the high aspect ratio trench without requiring changes to the overall trench geometry that would reduce transistor density.
3Ease of manufacture
If conventional metal gate etch-back process is used, then excess metal layers are removed, but punch-through defects occur due to trapped voids
Solution Approach 1:
The mandrel structure is formed before metal layer deposition, preventing void formation in the first place. This preliminary action eliminates the root cause of punch-through defects, allowing the subsequent etch-back process to proceed without encountering defects caused by trapped voids.
Solution Approach 2:
The mandrel structure, which occupies space in the gate trench, actually benefits the process by providing a template for uniform metal deposition. After the metal layers are formed, the mandrel is removed, and the previously occupied space is now filled with uniform metal, converting the mandrel's presence from a space-consuming element to a quality-enhancing tool that prevents punch-through defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enhances the uniformity and integrity of gate metal layers, reducing defects and improving transistor performance by preventing seam trapping during the metal gate etch-back process.
Implementation Method 1
depositing a gate dielectric layer and a work function layer in the gate trench
Implementation Method 2
depositing a gate dielectric layer and a work function layer in the gate trench
Implementation Method 3
passivating a surface portion of the capping layer to form a passivation layer
Data Source
AI summary
A semiconductor device includes a channel region over a substrate, first and second source/drain regions sandwiching the channel region, a metal gate over the channel region and disposed between the first and second source/drain regions, and a gate spacer extending along a sidewall of the metal gate. The metal gate includes a gate dielectric layer, a work function layer over the gate dielectric layer, a capping layer over the work function layer, a metal-containing film surrounded by the capping layer, and a fill layer surrounded by the metal-containing film.