Metal Gate Structure with Variable Thickness Work Function Layers
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Solution Overview
Problem
The 'gate last' process in CMOS fabrication faces challenges with high gate resistance due to multiple work-function layers in metal gate structures, leading to device instability and failure, especially as feature sizes decrease.
Innovation Solution
A method is developed to form semiconductor devices with a metal gate structure by creating layers of metallic compounds with varying thicknesses and using sacrificial layers to pattern and remove materials, reducing the complexity of work-function layer formation and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple work-function layers are used in metal gate structure, then gate electrode performance is improved, but gate resistance increases causing device instability and failure
Solution Approach 1:
The patent extracts and removes the problematic multiple work-function layers from the metal gate structure, replacing them with a single-layer work function metal layer that achieves the desired gate performance without the harmful high resistance effects of multiple layers
Solution Approach 2:
The patent uses composite material structure with a single-layer work function metal layer combined with metal gate electrodes of different materials (first and second metal gate electrodes with different work functions) to achieve both low resistance and proper gate performance
2Productivity
If feature sizes are decreased to improve integration, then device density increases, but gate resistance problems are exacerbated
Solution Approach 1:
The patent changes the material parameters by using different metal materials for the first and second gate electrodes, each with specific work function values, to optimize electrical performance at reduced feature sizes without suffering from high resistance
Solution Approach 2:
The patent removes the problematic multiple work-function layers that become increasingly harmful at smaller feature sizes, replacing them with a simplified single-layer structure that scales better to reduced dimensions
Data Source
AI summary
The disclosure relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a semiconductor device comprises a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; and an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness.