Metal Gate Dielectric Shapes to Prevent Voids in Core and I/O Regions
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Solution Overview
Problem
Current semiconductor fabrication techniques for high-k metal gate transistors face challenges due to the predetermined thickness of interfacial layers, leading to issues such as void formation in device regions like input/output and core regions, caused by the wet etching process during polysilicon gate removal.
Innovation Solution
A method is developed to fabricate semiconductor devices by forming first and second metal gates on the core and I/O regions, respectively, with gate dielectric layers having different shapes. Specifically, the first gate dielectric layer has an I-shape, and the second gate dielectric layer has a U-shape, allowing for tailored thickness and structure to address void formation issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a predetermined thickness interfacial layer is used in high-k metal gate transistor fabrication, then the gate structure can be simplified, but voids are formed due to epitaxial layer loss during wet etching process
Solution Approach 1:
The patent applies local quality by forming different gate dielectric layer structures in different regions: the first gate dielectric layer has a first thickness in the core region and a second thickness in the I/O region, with the first thickness being greater than the second thickness. This regional differentiation addresses the void formation issue in specific areas while maintaining overall device performance.
Solution Approach 2:
The patent changes the thickness parameter of the gate dielectric layer across different regions. By making the first thickness greater than the second thickness, the patent prevents void formation in the core region while maintaining appropriate gate control in the I/O region, thus resolving the contradiction between simplified structure and reliability.
2Ease of manufacture
If polysilicon gate is used, then fabrication process is conventional and simple, but boron penetration and depletion effect occur which increases equivalent thickness and reduces gate capacitance
Solution Approach 1:
The patent changes the material composition of the gate electrode from conventional polysilicon to a metal gate structure comprising a work function metal layer and a fill metal layer. This material parameter change eliminates boron penetration and depletion effects, maintaining high gate capacitance while enabling new fabrication approaches.
Solution Approach 2:
The patent uses a composite metal gate structure with multiple layers: a work function metal layer (first metal layer) and a fill metal layer (second metal layer). This composite structure combines the benefits of work function control with ease of fabrication, replacing the conventional single-material polysilicon gate.
3Ease of manufacture
If uniform gate dielectric layer thickness is used across all regions, then fabrication process is simplified, but device performance is affected due to different requirements of core and I/O regions
Solution Approach 1:
The patent implements local quality by creating region-specific gate dielectric thickness: the first gate dielectric layer has a first thickness in the core region and a second thickness in the I/O region. This allows optimization for each region's specific performance requirements while using a unified fabrication approach.
Solution Approach 2:
The patent segments the gate dielectric layer into different thickness regions. The first gate dielectric layer is formed with varying thickness across the substrate, with thicker portions in the core region and thinner portions in the I/O region, allowing independent optimization of each segment's performance.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of first providing a substrate having a core region and an input/output (I/O) region and then forming a first metal gate on the core region and a second metal gate on the I/O region. Preferably, the first metal gate includes a first gate dielectric layer, the second metal gate includes a second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer having different shapes such that the first gate dielectric layer includes an I-shape and the second gate dielectric layer includes a U-shape.