Metal Gate Width Adjustment for Parasitic Capacitance Reduction
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Solution Overview
Problem
In semiconductor devices, particularly those using MOS transistors, it is challenging to reduce parasitic capacitance between the gate line and the substrate as transistors become more highly integrated, and existing manufacturing processes require multiple masks and high-temperature steps, leading to inefficiencies and contamination issues with metal gate processes.
Innovation Solution
A semiconductor device and method that involves forming a fin-shaped silicon layer, a pillar-shaped silicon layer, and a metal gate electrode with a gate-last process, using a single mask for contact formation and reducing parasitic capacitance by adjusting the width of the metal gate electrode and pad to be larger than the metal gate line, and implementing a series of steps including impurity implantation, polysilicon gate formation, and metal deposition to minimize capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate is formed early in the process, then the gate resistance is reduced and depletion is suppressed, but metal contamination occurs in subsequent high temperature processes
Solution Approach 1:
The patent forms a placeholder gate structure (polysilicon or other material) before high temperature processes to protect against metal contamination, then replaces it with metal gate material after the high temperature processes are complete. This preliminary placeholder structure prevents contamination while allowing subsequent metal gate formation.
Solution Approach 2:
The patent uses an intermediary placeholder gate material (such as polysilicon) that can withstand high temperature processes without causing contamination. This intermediary structure performs the gate function temporarily and is later replaced by the final metal gate structure.
2Ease of manufacture
If polysilicon is used for the gate electrode, then the process is simpler, but the gate resistance is high and depletion occurs
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal, which fundamentally alters the electrical properties by reducing resistance and preventing depletion. This material parameter change resolves the performance limitations of polysilicon gates.
3Reliability
If a first insulating film is formed around the fin-shaped semiconductor layer, then parasitic capacitance is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent combines the formation of the first insulating film with other process steps, such as integrating it with the gate electrode formation process or combining multiple functional layers into a single deposition step. This merging approach reduces parasitic capacitance while minimizing the increase in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance between the gate line and the substrate, simplifies the manufacturing process by using a single mask for contact formation, and avoids contamination issues, enhancing the integration and performance of semiconductor devices.
Implementation Method 1
reduces parasitic capacitance between the gate line and the substrate
Implementation Method 2
implantation, polysilicon gate formation
Data Source
AI summary
A semiconductor device includes a fin-shaped silicon layer on a silicon substrate. A first insulating film is around the fin-shaped silicon layer and a pillar-shaped silicon layer is on the fin-shaped silicon layer. A gate insulating film is around the pillar-shaped silicon layer. A metal gate electrode is around the gate insulating film and a metal gate line is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, and a width of the metal gate electrode and a width of the metal gate pad is larger than a width of the metal gate line.