Metal Gate Work Function Layers for FinFET Leakage Reduction
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Solution Overview
Problem
Current methods for forming metal gates in multi-gate field effect transistors face challenges due to the difficulty in depositing conformal work function metal layers in three-dimensional structures, leading to increased current leaks and power consumption.
Innovation Solution
The method involves forming a high-k dielectric material on a semiconductor substrate, depositing a high-k dielectric cap layer, and using atomic layer deposition or chemical vapor deposition to create thin metal films with specific work function layers and cap layers, including TiN, TiSiN, or TiAlN, to achieve conformal deposition and prevent oxidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If physical vapor deposition (PVD) techniques are used for work function metal deposition, then the deposition process is simple and fast, but it is exceedingly difficult to deposit thin conformal films in three-dimensional gate structures
Solution Approach 1:
The patent replaces physical vapor deposition (PVD) with chemical vapor deposition (CVD) techniques. Specifically, it uses atomic layer deposition (ALD) for the high-k dielectric material and cap layer, and CVD for the work function metal layers. This substitution enables conformal film deposition in three-dimensional FinFET gate structures, resolving the contradiction between process simplicity and deposition quality.
2Reliability
If gate oxide thickness is reduced to increase channel conductivity, then transistor performance improves when on, but quantum mechanical electron tunneling occurs leading to increased power consumption
Solution Approach 1:
The patent changes the dielectric constant parameter by replacing traditional silicon dioxide gate oxide with high-k dielectric materials having dielectric constants of 25 or greater. This allows the gate dielectric to be made thicker than conventional 1.2 nm oxides while maintaining equivalent electrical performance, thereby preventing electron tunneling and reducing power consumption while preserving channel conductivity.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials combined with metal gate electrodes and work function metal layers. This composite approach enables simultaneous optimization of gate control, conductivity, and leakage prevention, resolving the contradiction between performance and power consumption.
3Ease of manufacture
If traditional planar transistor structures are used, then manufacturing is simpler, but current leaks increase as transistor size decreases
Solution Approach 1:
The patent transitions from two-dimensional planar transistor structures to three-dimensional FinFET structures where the channel is raised as a thin fin extending from the substrate and the gate is draped over the channel on three sides. This dimensional change constrains current to the raised channel and abolishes leakage paths, resolving the contradiction between manufacturing simplicity and current leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of metal gates with improved conductivity and reduced leakage currents, allowing for more efficient and reliable operation of multi-gate transistors, particularly in technology nodes beyond 15 nm.
Implementation Method 1
depositing a high-k dielectric cap layer, and using atomic layer deposition or chemical vapor deposition to create thin metal films
Implementation Method 2
using atomic layer deposition or chemical vapor deposition to create thin metal films
Implementation Method 3
forming a high-k dielectric material on a semiconductor substrate... The gate dielectric typically comprises a thin material layer having a dielectric constant of about 4.0 or greater
Implementation Method 4
Current methods utilize physical vapor deposition (PVD) techniques for work function metal
Data Source
Figure 1
AI summary
Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.