Metal Gate Work Function Engineering for Memory Cell Erase Speed
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Solution Overview
Problem
Integrated circuits (ICs) face challenges with small operation windows and slow erase speeds due to low work function polysilicon control gate electrodes, leading to electron back gate injection and high erase saturation, which affects manufacturing yields and costs.
Innovation Solution
Implementing a memory cell with a metal control gate electrode having a p-type work function, combined with high κ gate dielectrics, to enhance erase speed and operation window resilience, while allowing integration into existing IC processes without additional reticles or photomasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon control gate electrode with low work function is used, then manufacturing process is simple, but operation window is small and erase speed is slow
Solution Approach 1:
The patent changes the work function parameter of the control gate electrode from low (polysilicon) to high (metal with p-type work function). This parameter change directly improves erase speed by preventing electron back gate injection, while the metal gate can be integrated into existing HKMG manufacturing processes
Solution Approach 2:
The patent uses a composite structure combining metal control gate electrode with high-κ gate dielectric layers. This composite material approach enables both high erase speed (from metal gate's high work function) and manufacturability (through integration with existing high-κ metal gate processes)
2Ease of manufacture
If polysilicon control gate electrode with low work function is used, then manufacturing process is simple, but operation window is small
Solution Approach 1:
The patent changes the work function parameter from low to high by using metal with p-type work function. This increases the operation window by preventing electron back gate injection during erase operations, while maintaining compatibility with existing manufacturing processes through HKMG technology integration
Solution Approach 2:
The patent uses metal gate electrodes that can be formed through existing HKMG processes, replacing the need for specialized polysilicon processing. This maintains manufacturing simplicity while achieving improved device performance through the inherent properties of metal gates
3Speed
If metal control gate electrode with p-type work function is used, then erase speed is improved, but device complexity increases
Solution Approach 1:
The patent makes the control gate electrode universal by using metal that can serve both as the control gate for memory cells and as part of the high-κ metal gate structure. This multi-functionality reduces device complexity by eliminating the need for separate polysilicon gate structures, as the metal gate fulfills both roles within the existing HKMG framework
4Reliability
If metal control gate electrode with p-type work function is used, then resilience to process variations is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes from polysilicon to metal gate electrode, which provides better resilience to process variations due to the inherent stability of metal work functions. The high-κ metal gate formation processes already in place provide controlled precision for metal deposition, balancing the improved reliability with existing manufacturing capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a larger operation window, improved resilience to process variations and noise, and the ability to scale for advanced process nodes like 28 nm and smaller, with uniform performance parameters during bulk manufacturing.
Implementation Method 1
a control gate electrode, a charge trapping layer, and a control gate dielectric layer stacked on the control gate well... The control gate electrode may be or comprise a first metal with a p-type work function
Data Source
AI summary
Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.