Metal Gate Work Function Tuning for Threshold Voltage Control
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Solution Overview
Problem
Current semiconductor manufacturing faces challenges in achieving transistors with multiple threshold voltages due to insufficient gate trench space, which restricts the thickness and composition of metal gate elements, affecting the performance and compatibility of CMOS devices.
Innovation Solution
A novel semiconductor device design and manufacturing method that allows for the concurrent production of transistors with the same conductive type but different threshold voltages by forming distinct layers and structures within the same process, including high-k dielectric layers, bottom barrier metals, work function metals, and low resistance metals, to tune the threshold voltages effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual metal gate method is used to achieve different threshold voltages, then transistor performance is improved, but gate trench space becomes insufficient and process complexity increases
Solution Approach 1:
The patent applies local quality by forming different work function metal layers in different regions of the semiconductor device. Specifically, a first work function metal layer is formed in a first region while a second work function metal layer is formed in a second region, allowing each region to have locally optimized electrical characteristics. This enables different threshold voltages to be achieved in different transistor regions without requiring complex dual metal gate processes throughout the entire device, thus improving transistor performance while controlling process complexity.
2Length of moving object
If gate trench space is reduced to accommodate smaller features, then device scaling is achieved, but thickness and composition control of metal gate elements becomes more difficult
Solution Approach 1:
The patent segments the gate structure into multiple distinct layers including a high-k dielectric layer, a first work function metal layer, and a second work function metal layer. This segmentation allows each layer to be independently formed and controlled through separate deposition processes. By dividing the gate structure into manageable segments, the patent enables precise control of each layer's thickness and composition even as the overall gate critical dimension is reduced for device scaling, thereby maintaining manufacturing precision while achieving smaller feature sizes.
3Ease of manufacture
If polysilicon gate is used, then manufacturing is simplified, but boron penetration and depletion effect worsen device performance
Solution Approach 1:
The patent extracts the problematic boron doping step from the gate fabrication process by replacing the conventional polysilicon gate with a metal-based gate structure consisting of high-k dielectric and work function metal layers. This extraction eliminates the boron penetration and depletion effects that plague polysilicon gates, as the metal gate structure does not require boron doping to achieve the desired work function. The result is improved device performance while the multi-layer metal gate structure can still be manufactured using standard deposition techniques, maintaining reasonable ease of manufacture.
Data Source
AI summary
A method of manufacturing semiconductor devices, including the steps of providing a substrate with a first active region, a second active region and a third active region, forming dummy gates in the first active region, the second active region and the third active region, removing the dummy gates to form trenches in the first active region, the second active region and the third active region, forming a high-k dielectric layer, a first bottom barrier metal layer on the high-k dielectric layer, a second bottom barrier metal layer on the first bottom barrier metal layer, and a first work function metal layer on the second bottom barrier metal layer in the trenches, removing the first work function metal layer from the second active region and the third active region, removing the second bottom barrier metal layer from the third region, and filling up each trench with a low resistance metal.