Metal Gate Work Function Variation via High Pressure Anneal
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Solution Overview
Problem
Current semiconductor fabrication techniques face issues with device mismatch and performance degradation due to boron penetration and depletion effects in polysilicon gates, leading to variations in work function and device performance, especially when NMOS and PMOS transistors are adjacent to each other.
Innovation Solution
A method involving a replacement metal gate process with a high-k dielectric layer, work function metal, and top barrier metal layers, followed by a high pressure anneal process using hydrogen gas to improve work function variation, including specific layer thicknesses and processing conditions to minimize barrier layer thickness and optimize metal gate performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon gate is used, then gate electrode can be formed, but boron penetration and depletion effect occur leading to work function variation and device performance degradation
Solution Approach 1:
The patent extracts and removes the polysilicon gate material that causes boron penetration and depletion effects. Instead, a metal gate structure is implemented that eliminates these harmful interactions while maintaining the gate electrode function, thereby resolving the technical contradiction between device performance and harmful effects.
Solution Approach 2:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, titanium nitride, or tantalum nitride). This material substitution fundamentally alters the electrical and chemical properties, eliminating boron penetration and depletion effects while providing stable work function characteristics.
2Manufacturing precision
If high-k metal gate is used, then work function control is improved, but device mismatch occurs between adjacent NMOS and PMOS transistors
Solution Approach 1:
The patent applies different metal materials or compositions to different regions (NMOS and PMOS gates) to achieve locally optimized work functions. By tailoring the metal gate composition specifically for each transistor type, precise work function control is achieved while ensuring matching characteristics between adjacent devices.
Solution Approach 2:
The patent implements preliminary work function adjustment through controlled annealing processes and metal gate formation techniques before final device assembly. This preliminary optimization ensures that work function variations are minimized early in the fabrication process, preventing device mismatch in subsequent stages.
3Manufacturing precision
If metal gate is formed with thin barrier layer, then work function variation is reduced, but process control difficulty increases
Solution Approach 1:
The patent employs composite metal gate structures combining multiple metal layers (such as tungsten/titanium nitride/tantalum nitride combinations) with carefully controlled thickness ratios. This composite approach achieves precise work function control through material composition rather than relying solely on thin barrier layer dimensions, thereby reducing process control difficulty.
Solution Approach 2:
The patent shifts the control parameter from barrier layer thickness to metal composition ratio and annealing temperature. By changing the dominant control parameter from dimensional precision to compositional control and thermal processing, work function variation is reduced while maintaining easier process control through well-established semiconductor manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces work function variation and improves device performance by minimizing threshold voltage and current mismatches between adjacent transistors, enhancing the overall reliability and efficiency of semiconductor devices.
Implementation Method 1
forming a high-k dielectric layer in the recess
Implementation Method 2
performing a high pressure anneal (HPA) process for improving work function variation of the metal gate
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; forming an inter-metal dielectric (IMD) layer on the metal gate; forming a metal interconnection in the IMD layer; and performing a high pressure anneal (HPA) process for improving work function variation of the metal gate.