Metal-Insulator-Metal Capacitor in Interconnection Stack
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Solution Overview
Problem
Conventional methods for forming capacitive metal-insulator-metal structures in integrated circuit interconnection stacks result in high series resistance, limiting high-frequency performance and requiring additional interconnection levels, while also restricting the use of metallization above capacitive structures due to short-circuit risks.
Innovation Solution
A method for forming a three-dimensional capacitive metal-insulator-metal structure directly in a metal level of an interconnection stack, involving the formation of a trench in a conductive track, conformal deposition of insulating and conductive layers, and planarization, which allows for increased capacitance per surface area and reduces access resistance by integrating the capacitive structure within a metal track.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitive structure is formed in via level before metal level, then capacitive structure can be integrated, but series resistance increases and high-frequency performance is limited
Solution Approach 1:
The patent transitions from forming capacitive structures in the via level (conventional approach) to forming them directly in the metal level. This dimensional repositioning allows the capacitive structure to be integrated within the metal track itself, reducing access resistance and improving high-frequency performance by eliminating the need for separate via-level capacitor structures with their associated resistance penalties.
Solution Approach 2:
The patent merges the capacitive structure formation with the metal level formation process. Instead of creating capacitors as separate entities in the via level and then adding metal levels above them, the invention integrates the capacitive structure directly within the metal level, combining multiple functions into a single integrated structure that reduces overall resistance.
2Productivity
If conventional capacitive structure formation is used, then integration is achieved, but additional interconnection levels are required
Solution Approach 1:
The patent makes the metal level serve multiple functions: it provides both the interconnection function (metal tracks) and the capacitive function (integrated capacitive structures). This multi-functionality eliminates the need for separate via-level capacitor structures and reduces the total number of interconnection levels required, thereby improving productivity and reducing device complexity.
Solution Approach 2:
The capacitive structure is formed during the metal level fabrication process itself, rather than requiring additional subsequent steps. By integrating capacitor formation into the existing metal level creation sequence, the patent eliminates the need for additional interconnection levels and process steps, improving integration efficiency.
3Ease of operation
If metal track is used above capacitive structure, then connection is achieved, but short-circuit risk limits metallization usage
Solution Approach 1:
The patent extracts the capacitive structure from the via level and relocates it directly within the metal level. This repositioning eliminates the need for metal tracks to be placed above capacitive structures, as the capacitor is now integrated within the metal level itself. The metal track and capacitive structure are formed simultaneously in the same level, eliminating short-circuit risks while maintaining full metallization utilization.
4Reliability
If capacitive structure is formed in trench, then capacitance is achieved, but access resistance at walls is significant
Solution Approach 1:
The patent changes the spatial arrangement by forming the capacitive structure directly within the metal level rather than in a trench in the via level. This dimensional repositioning allows the capacitive electrodes to be formed as horizontal layers within the metal track cross-section, eliminating the vertical wall access paths that create high resistance in conventional trench-based capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances capacitance per surface area unit and reduces access resistances, enabling the capacitive structure to operate effectively at higher frequencies and allowing full utilization of the metal level surface, thus overcoming the limitations of conventional methods.
Implementation Method 1
conformal deposition of insulating and conductive layers
Implementation Method 2
conformal deposition of insulating and conductive layers
Data Source
AI summary
A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.