Metal-Insulator-Metal Capacitor Stack for DRAM
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Solution Overview
Problem
Existing DRAM capacitors face challenges in meeting increasing capacitance demands due to their small capacitance area and high latency, which is exacerbated by the incompatibility of high-k dielectric materials with wafer processing techniques and the need for frequent charge refreshing.
Innovation Solution
A capacitor design featuring a metal-insulator-metal stack with a high-k dielectric material, such as hafnium oxide, is implemented, where the capacitance area is increased by adjusting the distances between the electrically conducting layers and insulating layers, allowing for a larger surface area and improved performance without compromising processing compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-k dielectric materials are used to increase capacitance, then capacitance area is improved, but processing compatibility deteriorates
Solution Approach 1:
The patent adjusts the physical parameters of the capacitor structure, specifically the distances between conducting layers and insulating layers, to optimize capacitance area while maintaining compatibility with existing wafer processing techniques. This allows achieving higher capacitance without compromising manufacturability.
Solution Approach 2:
The patent transitions from traditional planar capacitor structures to a stacked metal-insulator-metal configuration, utilizing vertical dimensionality to increase capacitance area. This dimensional change enables higher capacitance density while remaining compatible with standard processing workflows.
2Quantity of substance
If capacitor size is increased to meet capacitance demands, then capacitance area is improved, but device complexity increases
Solution Approach 1:
By stacking multiple conducting and insulating layers vertically, the patent increases capacitance area without expanding the lateral footprint. This vertical stacking approach meets capacitance demands while maintaining compact device geometry and manageable structural complexity.
Solution Approach 2:
The patent employs a composite metal-insulator-metal stack structure, combining different materials layers to achieve high capacitance. This composite approach allows optimization of each layer's properties while maintaining overall structural simplicity and compatibility with existing fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the capacitance area of the capacitor, effectively addressing the capacitance demands while minimizing charge leakage and processing issues, thereby improving the overall performance of DRAM cells.
Implementation Method 1
A capacitor design featuring a metal-insulator-metal stack with a high-k dielectric material, such as hafnium oxide, is implemented, where the capacitance area is increased
Implementation Method 2
high-k dielectric material, such as hafnium oxide
Data Source
AI summary
A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.