Metal Interconnect Cavity Structure for Low-Parasitic BEOL Transistors
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Solution Overview
Problem
Front-end-of-line (FEOL) transistors pose a bottleneck in achieving higher density non-volatile memories due to the need for larger transistors or multiple transistors in parallel to support high write currents, leading to increased FEOL area penalties, while placing access control devices in metal interconnects increases parasitic capacitance.
Innovation Solution
Incorporating cavities within dielectric structures in metal interconnects to reduce parasitic capacitance by etching high aspect ratio trenches and using distinct dielectric materials for the cavity edges, which are formed by selective etching of a middle layer, thereby reducing capacitive coupling between conductive features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If access control devices are placed in metal interconnects, then substrate space utilization is improved, but parasitic capacitance increases
Solution Approach 1:
The dielectric structure is segmented by introducing cavities that divide the continuous dielectric material into separate regions. This segmentation reduces the parasitic capacitance between conductive features while maintaining the compact layout that improves substrate space utilization.
Solution Approach 2:
The dielectric structure incorporates cavities that create a porous or hollow configuration. This porous dielectric structure reduces the effective dielectric constant and parasitic capacitance between conductors, allowing access control devices to be placed in metal interconnects without excessive capacitance penalties.
2Power
If FEOL transistors are made larger or multiple transistors are used in parallel, then write current capability is improved, but FEOL area increases
Solution Approach 1:
The patent moves access control devices from the FEOL to the BEOL (back-end-of-line) metal interconnects, utilizing the vertical dimension and higher layers of the interconnect structure. This dimensional transition allows high write current capability to be achieved without increasing the FEOL area, as the access devices are placed in subsequent processing layers.
3Object-generated harmful factors
If high aspect ratio trenches are etched to form cavities, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
A liner material is introduced as an intermediary substance that coats the walls of high aspect ratio trenches during cavity formation. This liner prevents trench collapse and facilitates the etching process, making it feasible to create the deep cavities needed for parasitic capacitance reduction without excessive manufacturing complexity.
Solution Approach 2:
The patent modifies physical parameters such as introducing liners and adjusting etch conditions to enable the formation of high aspect ratio trenches. By changing these parameters, the manufacturing process can achieve the deep cavity structures necessary for reducing parasitic capacitance while maintaining process feasibility.
Data Source
AI summary
An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.