Metal Interconnect Dishing Elimination via Seed Layer Roughening

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Solution Overview

Problem

The dishing effect, which results in non-planar surfaces and increased resistance in metal interconnects, is a persistent issue in semiconductor manufacturing due to the limitations of chemical mechanical planarization (CMP) processes, affecting the performance and resolution of subsequent photolithographic steps and device formation.

Innovation Solution

A method involving surface treatment to create rough surfaces on seed layers outside of trenches, followed by metal layer deposition, where the inferior quality of the metal layer on rough surfaces facilitates easier removal, ensuring the trenches are filled with a flat, dishing-free layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If chemical mechanical planarization (CMP) is used to planarize the copper layer, then the surface flatness is improved, but dishing defects (concavities or depressions) are formed in the copper layer

Engineering Contradiction:
Improvesurface flatnessVSAvoiddishing defects
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

A sacrificial layer is formed at the bottom of the trench before filling with copper material. This preliminary structure prevents the CMP process from creating dishing defects by providing a protective layer that maintains surface integrity during planarization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial layer acts as an intermediary between the trench bottom and the copper filling. It mediates the interaction during CMP processing, preventing direct contact between the CMP tools and the copper layer that would cause dishing, while still allowing proper copper deposition and electrical connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If higher conductive materials such as copper are used, then the conductance is improved, but the dishing effect increases and resistance increases

Engineering Contradiction:
ImproveconductanceVSAvoiddishing effect
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The sacrificial layer is deposited before copper filling to preemptively prevent dishing defects. This allows the use of high-conductivity copper material while maintaining surface flatness and preventing the formation of concavities that would increase resistance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial layer, which occupies space in the trench, is removed after copper filling to create a slightly enlarged trench space. This compensates for any potential dishing and ensures the copper interconnect maintains optimal electrical properties without resistance increases from surface defects.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If the trench is completely filled with metal layer, then the conductive path is improved, but dishing defects are formed in the filled metal

Engineering Contradiction:
Improveconductive pathVSAvoidflatness of filled trench
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The sacrificial layer is formed before copper deposition to establish a protective structure at the trench bottom. This preliminary structure ensures that when the trench is filled with copper, the CMP process will not create dishing defects, maintaining both complete filling and surface flatness.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial layer serves as a mediator during the copper filling and CMP processes. It protects the copper material from direct CMP action that would cause dishing, while still allowing complete trench filling for optimal conductive path formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9779989B1Method for manufacturing metal interconnects
Publication Date: 2017.10.03 MARLIN SEMICON LTD
  • US9779989B1 patent drawing
  • US9779989B1 patent drawing
  • US9779989B1 patent drawing

AI summary

A method for manufacturing metal interconnects. The method includes following steps. A substrate including a dielectric layer formed thereon is provided, and a plurality of trenches are formed in the dielectric layer. Next, a seed layer is formed in the trenches and on the dielectric layer and followed by masking regions of the seed layer to define a plurality of masked regions and a plurality of exposed regions for the seed layer. Subsequently, a surface treatment is performed to the exposed regions of the seed layer to form a plurality of rough surfaces on the exposed regions of the seed layer. Then, a metal layer is formed on the substrate, and the trenches are filled up with the metal layer.