Metal-Containing Interconnects for DRAM Pillar Contact Uniformity
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Solution Overview
Problem
Current methods for fabricating highly-integrated DRAM face challenges in forming efficient connections between digit-line-contact-regions and storage-element-contact-regions, particularly in achieving reliable interconnects with low resistance and high uniformity in tight circuitry configurations.
Innovation Solution
The method involves forming connections using metal-containing interconnects, such as ruthenium over cobalt silicide, directly contacting monocrystalline silicon, and employing epitaxial growth of silicon to reduce resistance and improve uniformity, along with the use of insulative spacers and barrier materials to enhance integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional interconnect methods are used in highly-integrated DRAM, then device complexity is reduced, but manufacturing precision and reliability of interconnects deteriorate due to tight circuitry configurations
Solution Approach 1:
The interconnect structure is segmented into multiple functional layers: a first interconnect layer with digit line contacts, a second interconnect layer with storage element contacts, and intermediate connection structures. This segmentation allows each layer to be optimized independently for its specific function, achieving high manufacturing precision in tight circuitry configurations without excessive device complexity.
Solution Approach 2:
The patent transitions from planar interconnect arrangements to three-dimensional vertical stacking of interconnect layers. By utilizing the vertical dimension, the design achieves high integration density while maintaining reliable electrical connections, as each interconnect layer can be formed with precise control over thickness and composition independent of lateral spacing constraints.
2Productivity
If interconnects are formed in tight circuitry configurations, then device integration is improved, but resistance and non-uniformity increase
Solution Approach 1:
The interconnects are formed as composite structures with multiple materials having different properties. The first interconnect layer uses a material optimized for digit line connections, while the second interconnect layer uses a material optimized for storage element connections. This composite approach allows simultaneous optimization of electrical performance and integration density, achieving low resistance and high uniformity despite tight circuitry configurations.
Solution Approach 2:
Different regions of the interconnect structure are assigned different material compositions and geometries optimized for their specific local functions. The digit line contacts, storage element contacts, and intermediate connections each have tailored properties that minimize resistance and maximize reliability in their respective locations, enabling high device integration without compromising interconnect performance.
3Manufacturing precision
If metal-containing interconnects are used directly on monocrystalline silicon, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The first interconnect layer and digit line contacts are formed preliminarily before the second interconnect layer and storage element contacts. This preliminary action establishes a stable foundation that simplifies subsequent processing steps, as the initial interconnect structure provides defined contact points and electrical pathways that guide the formation of the second layer, achieving high manufacturing precision without excessive overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of efficient and reliable interconnects that improve the integration and performance of DRAM by reducing resistance and enhancing uniformity, particularly in the tight confines of highly-integrated circuitry.
Implementation Method 1
Cobalt silicide is directly against silicon of one or more of the contact regions
Implementation Method 2
Metal-containing material is directly against the cobalt silicide
Implementation Method 3
employing epitaxial growth of silicon to reduce resistance and improve uniformity
Data Source
AI summary
Some embodiments include an integrated assembly having active-region-pillars. Each of the active-region-pillars has contact regions. The contact regions include a pair of storage-element-contact-regions, and include a digit-line-contact-region between the storage-element-contact-regions. The active-region-pillars include silicon. Wordlines are along the active-region-pillars and extend along a first direction. Cobalt silicide is directly against the silicon of one or more of the contact regions. Metal-containing material is directly against the cobalt silicide. Digit-lines are electrically coupled with the digit-line-contact-regions and extend along a second direction which crosses the first direction. Storage-elements are electrically coupled with the storage-element-contact-regions. Some embodiments include methods of forming integrated assemblies.