Metal Interconnect Self-Forming Cap for Electromigration and RC Delay
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Solution Overview
Problem
The increasing current density through metal interconnects in semiconductor structures due to shrinking dimensions requires improved electromigration resistance, but conventional metal capping layers can lead to metallic residues and increased capacitance, causing leakage and RC delay issues.
Innovation Solution
A semiconductor structure with a self-forming metal capping layer that eliminates the need for selective deposition, thereby preventing metallic residues and using a self-aligned etching stop layer to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal capping layer is formed using selective deposition process to improve electromigration resistance, then electromigration lifetime is improved, but metallic residues are formed on the interface between interlayer dielectric layer and etching stop layer causing leakage
Solution Approach 1:
The patent removes the metal capping layer from the selective deposition process entirely. Instead, a dielectric capping layer is used to cap the metal interconnect, which eliminates the formation of metallic residues at the interface while still providing the necessary protection and electromigration resistance through the dielectric material configuration.
Solution Approach 2:
The patent replaces the metal capping layer with a dielectric capping layer that serves the protective function without the harmful side effects. The dielectric material acts as a temporary or permanent protective layer that can be integrated into the standard dielectric stack without requiring complex selective deposition processes.
2Manufacturing precision
If a conformal etching stop layer with higher dielectric constant is used to stop the etching, then etching selectivity is improved, but higher capacitance is caused resulting in increased interconnection RC delay
Solution Approach 1:
The patent applies different dielectric constant values to different regions or layers of the etching stop structure. By using a lower dielectric constant material for the etching stop layer that is in direct contact with the metal interconnect, the parasitic capacitance is reduced while still maintaining adequate etching selectivity through the layered dielectric structure.
Solution Approach 2:
The patent employs a composite dielectric structure for the etching stop layer, combining multiple dielectric materials with different properties. This composite structure provides both the necessary etching selectivity and reduced parasitic capacitance by strategically placing materials with appropriate dielectric constants in different positions within the etching stop layer stack.
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes the following steps. A trench is formed in a first interlayer dielectric (ILD) layer. A metal conductor with metal dopants is filled in the trench. Planarization is performed on the metal conductor with the metal dopants. A thermal treatment, a photo treatment or a bias-assist treatment is performed on the metal conductor with the metal dopants to form a self-forming metal capping layer on a first metal layer. An etching stop bi-layer structure is formed on the first interlayer dielectric layer and the self-forming metal capping layer. A via, a second interlayer dielectric (ILD) layer and a second metal layer are formed on the etching stop bi-layer structure. The via is embedded in the second interlayer dielectric layer and the via is disposed between the first metal layer and the second metal layer.