Metal Interconnect Layout Fabrics for 10nm Via Overlay Control
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Solution Overview
Problem
Conventional fabrication processes face challenges in scaling integrated circuits to the 10 nanometer node or sub-10 nanometer range due to variability and limitations in lithographic processes, leading to issues with via overlay, critical dimension control, and line width roughness, which affect the manufacturability of metal interconnects.
Innovation Solution
A comprehensive layout design specification and methodology for generating semiconductor chip metal interconnect fabrics using configurations C1 thru C5, which cover the full design rule space, allowing for early testing of backend metallization processes on short-loop RECL test chips, incorporating various layout patterns and complexities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10nm node and below
Solution Approach 1:
The patent segments the interconnect fabrication process into multiple patterning steps (e.g., self-aligned double patterning, self-aligned quadruple patterning) where each step creates a portion of the final pattern. This segmentation enables precise via overlay at 10nm node by breaking down the complex single-step lithography into manageable sequential steps, each with controlled precision requirements.
Solution Approach 2:
The patent employs preliminary patterning actions where mandrel structures and spacer layers are formed in advance before the final interconnect pattern is created. These preliminary structures serve as self-aligned templates that guide subsequent etching steps, ensuring precise via overlay without requiring complex real-time alignment procedures.
2Productivity
If feature size is reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates due to variability
Solution Approach 1:
The patent implements self-aligned fabrication processes where each patterning step automatically aligns to previously formed structures without requiring additional alignment machinery or procedures. The spacer layers and mandrels serve as self-generated alignment references, eliminating overlay errors and ensuring consistent critical dimensions even at reduced feature sizes.
Solution Approach 2:
The patent changes the fabrication parameters by transitioning from direct single-step lithography to multi-step self-aligned processes. This parameter change includes using spacer thickness and mandrel dimensions as controlled variables that directly determine final interconnect dimensions, providing better control over critical dimensions at scaled feature sizes.
3Manufacturing precision
If new fabrication methodologies are introduced to improve precision, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent develops universal self-aligned patterning methodologies that can be applied across multiple interconnect layers and different device types. The same spacer-based approach and process flow are used for various line width requirements, reducing the need for layer-specific process variations and simplifying overall manufacturing despite the increased number of process steps.
Data Source
Figure 1~3A(c)
Figure 3B(a)~3C(b)
Figure 3D(a)~3E
AI summary
Voltage contrast (VC) image simulation capability and associated test structures are described. In an example, a circuit structure includes an inter-layer dielectric (ILD) layer. A plurality of unidirectional wires is in the ILD layer. In one specific example, the integrated circuit structure includes one or more additional wires in the ILD layer, the one or more additional wires along a direction different than a direction of the plurality of unidirectional wires, and the one or more additional wires are each continuous with a corresponding one of the plurality of unidirectional wires at a location between ends of the corresponding one of the plurality of unidirectional wires. In another specific example, one or more of the plurality of unidirectional wires have a line width transition therein.