Metal Interconnection Structure With Air Gaps for Lower RC Delay
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Solution Overview
Problem
The increasing integration of transistors in integrated circuits leads to higher metal wire resistance, interline capacitance, and interlayer capacitance, resulting in increased RC delay time, series noise, and power consumption, which existing technologies struggle to mitigate effectively due to the shrinking dimensions of trenches and vias in metal interconnection dual damascene processes.
Innovation Solution
A metal interconnection structure is developed with dielectric layers on both sides of the metal layers, having gaps with them, and a metal diffusion covering layer, which reduces parasitic capacitance and metal ion diffusion to the dielectric materials, ensuring structural integrity and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of metal wiring layers is increased to achieve high integration, then the integration of chips is improved, but the metal wire resistance, interline capacitance and interlayer capacitance increase, leading to increased RC delay time and power consumption
Solution Approach 1:
A dielectric layer with low dielectric constant (such as SiCOH) is introduced as an intermediary material between metal interconnection layers to reduce parasitic capacitance. Additionally, a metal diffusion barrier layer (such as TaN or TiN) is used as an intermediary to prevent metal ion diffusion while maintaining electrical performance
Solution Approach 2:
The patent employs composite material structures including multiple metal layers (copper and aluminum) with different properties, combined with dielectric materials (SiO2, SiCOH) and barrier materials (TaN, TiN) to achieve optimal balance between conductivity, capacitance reduction, and diffusion prevention
2Adaptability or versatility
If the transverse dimensions of trenches and vias are shrunk to increase integration, then the integration is improved, but the aspect ratio of trenches and vias increases, making manufacturing more difficult
Solution Approach 1:
The patent changes the dimensional parameters of the interconnection structure by optimizing trench width, via diameter, and layer thicknesses to maintain manufacturability while achieving high integration. The barrier layer thickness is specifically optimized to be thin enough to maintain volume but thick enough to prevent diffusion
3Adaptability or versatility
If the thicknesses of copper diffusion barrier layer and copper adhesion layer are reduced to maintain copper interconnection line volume, then the integration is improved, but the barrier property of the copper diffusion barrier layer is greatly weakened
Solution Approach 1:
The patent uses composite barrier structures with multiple materials (TaN, TiN) having different properties. The barrier layer is designed with specific thickness and material composition to achieve both thin profile for integration and sufficient barrier performance. The adhesion layer is optimized separately to ensure copper bonding while minimizing diffusion risk
Data Source
AI summary
The present invention provides a metal interconnection structure and a manufacturing method thereof, the metal interconnection structure includes: metal interconnection lines disposed at intervals, first metal layers respectively disposed on the metal interconnection lines; second metal layers respectively disposed on the first metal layers; dielectric layers disposed on both sides of the first metal layer and the second metal layer and having a gap with both the first metal layer and the second metal layer; and a metal diffusion covering layer covering the dielectric layer and the second metal layer. In the present invention, by disposing the dielectric layer on both sides of the first metal layer and the second metal layer, and the dielectric layer has a gap with both the first metal layer and the second metal layer, and the formed metal interconnection structure reduces parasitic capacitance due to the gap, and the gaps existing between the first metal layer and the dielectric layer and between the second metal layer and the dielectric layer can further reduce the diffusion of metal ions to the dielectric layer.


