Metal Interconnection Capping for Semiconductor Reliability
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Solution Overview
Problem
The reduction in critical dimension of semiconductor devices leads to increased resistance and capacitance in metal interconnections, making high-speed operation challenging, and existing solutions fail to effectively reduce these issues.
Innovation Solution
A method involving the formation of a low-k dielectric layer, conformal barrier metal layer, and selective deposition of a metal capping layer using chemical vapor deposition, where the metal capping layer thickness on the metal pattern is greater than on the low-k dielectric layer, to improve the reliability of metal interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimension of metal interconnections is reduced to achieve high integration, then the integration density is improved, but the resistance of metal interconnections increases
Solution Approach 1:
The patent changes the material parameter from aluminum to copper, which has inherently lower resistivity. This material substitution allows the interconnection to maintain low resistance even at reduced critical dimensions, thereby enabling high integration without sacrificing electrical performance
Solution Approach 2:
The patent employs a composite interconnection structure consisting of copper core with aluminum or copper alloy cladding layers. This composite approach combines the low resistivity of copper with the oxidation resistance and electromigration resistance of aluminum or copper alloys, achieving both low resistance and high reliability at scaled dimensions
2Productivity
If the critical dimension of metal interconnections is reduced to achieve high integration, then the integration density is improved, but the capacitance between metal interconnections increases
Solution Approach 1:
The patent introduces a new parameter - the dielectric constant of the interlayer insulating film - and changes it by using low-k dielectric materials. This reduction in dielectric constant directly decreases the capacitance between adjacent interconnections, allowing high integration density to be achieved without excessive capacitive coupling that would limit signal speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the resistance and dielectric constant of interconnections, enhancing the reliability and performance of semiconductor devices by preventing copper diffusion and improving electromigration properties.
Implementation Method 1
forming a metal capping layer on top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process
Data Source
AI summary
A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer.