Multi-Layer Metal Interconnection for Packing Density
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Solution Overview
Problem
In semiconductor process development, there is a challenge in achieving quick feedback on device performance and process margin during wafer acceptance tests at lower metal layers, especially as feature sizes scale down, leading to issues with metal thickness, aspect ratio, and packing density, which affects etching, deposition, and test robustness.
Innovation Solution
The semiconductor structure incorporates a multi-layer interconnection (MLI) design with specific thickness ratios and dimensional parameters for metal layers, including a second metal layer with greater thickness and pitch to enhance packing density and reduce intra-cell coupling capacitance, while maintaining robustness for wafer acceptance tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal layer thickness is increased to maintain aspect ratio for robust manufacturing, then manufacturing precision and process margin are improved, but test robustness and WAT reliability deteriorate due to high contact resistance, open circuits, and probe punching through
Solution Approach 1:
The patent introduces a third metal layer (M3) above the second metal layer (M2) to create a multi-layer interconnection structure. This dimensional addition allows the design to overcome the limitations of single-layer thickness optimization by distributing interconnection functions across multiple layers with different thickness characteristics, thereby simultaneously achieving manufacturability and test robustness
Solution Approach 2:
The patent applies different metal layer thicknesses at different locations and for different functions: M1 and M3 layers have thinner thickness optimized for test robustness and WAT, while M2 layer has greater thickness optimized for manufacturing aspect ratio control. This localized differentiation resolves the contradiction by allowing each layer to be optimized for its specific function
2Reliability
If metal layer thickness is decreased to improve test robustness and reduce contact resistance, then test reliability is improved, but manufacturing precision deteriorates due to insufficient process margin for etching and metal deposition
Solution Approach 1:
The patent segments the interconnection function across three separate metal layers (M1, M2, M3) with different thickness characteristics. M1 and M3 layers are thinner for test robustness, while M2 layer is thicker for manufacturing margin, allowing the system to achieve both test reliability and manufacturing precision through functional segmentation
Solution Approach 2:
By adding the M3 layer above M2, the patent creates a multi-dimensional interconnection structure that allows thin layers (for test robustness) to coexist with thick layers (for manufacturing margin) in different spatial dimensions, resolving the contradiction between thickness requirements
3Productivity
If feature sizes are scaled down to increase packing density, then productivity and chip density are improved, but device complexity and manufacturing difficulty increase due to high aspect ratio trenches and vias
Solution Approach 1:
The patent uses multiple metal layers stacked vertically to provide additional routing dimensions. This allows standard-cell logic circuits to achieve high packing density in the planar direction while using the vertical dimension (M1, M2, M3 layers) to manage interconnections, thereby reducing the complexity of high-aspect-ratio etching and deposition processes
Solution Approach 2:
The patent segments the interconnection function across multiple thin metal layers rather than using fewer thick layers. This segmentation allows each layer to have manageable thickness and aspect ratio, reducing manufacturing complexity while maintaining high overall packing density through efficient vertical stacking
Data Source
AI summary
The semiconductor structure includes a semiconductor substrate having active regions; field-effect devices disposed on the semiconductor substrate, the field-effect devices including gate stacks with elongated shape oriented in a first direction; a first metal layer disposed over the gate stacks, the first metal layer including first metal lines oriented in a second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, the second metal layer including second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, the third metal layer including third metal lines oriented in the second direction. The first, second, and third metal lines have a first thickness T1, a second thickness T2, and t a third thickness T3, respectively. The second thickness is greater than the first thickness and the third thickness.