Metal Landing Etch for Via Overlay Margin in Semiconductor Patterning
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Solution Overview
Problem
In semiconductor device fabrication, improved overlay control is challenging during metal etching due to reduced dimensions, leading to increased errors and formation of pits/voids in metal lines and vias, especially with the misalignment of lithography blocking layers.
Innovation Solution
A directional patterning technique is employed to increase the error margin in overlay control by removing portions of the hard mask layer surrounding the via, creating a metal landing margin, which widens the opening and exposes the upper surface of the insulating layer, thereby reducing the occurrence of pits or voids during metal etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If metal etching is performed with reduced dimensions, then device fabrication capability is improved, but overlay control deteriorates leading to increased errors and pits/voids
Solution Approach 1:
The patent applies preliminary action by performing a directional patterning etch on the hard mask layer before the main metal etching process. This pre-etching step creates a metal landing margin by removing portions of the hard mask surrounding the via, which establishes a buffer zone that compensates for potential overlay misalignment during subsequent metal deposition, thereby preventing pits and voids formation
Solution Approach 2:
The patent changes the etching parameters by introducing a directional patterning step with specific etch conditions (CHF3 plasma, controlled etch depth, and directional control) that modify the hard mask layer geometry. This parameter change creates a wider opening and exposes the insulating layer surface, providing a larger target area for metal deposition that improves overlay tolerance despite reduced feature dimensions
2Device complexity
If lithography blocking layer alignment is maintained, then overlay control is simplified, but error margin is reduced due to reduced dimensions
Solution Approach 1:
The directional patterning etch is performed in advance to create a metal landing margin that serves as a buffer against alignment errors. This preliminary modification of the hard mask layer geometry provides a larger effective target area for metal deposition, increasing the tolerance for lithography blocking layer misalignment without requiring more complex alignment procedures
Solution Approach 2:
The patent creates a cushioning effect by removing hard mask material surrounding the via to form a metal landing margin. This margin acts as a protective buffer zone that absorbs potential overlay errors, ensuring that even if alignment deviations occur during metal deposition, the metal will still land on the intended area without forming pits or voids
Data Source
AI summary
A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.