Metal Layer Aware IC Design Optimization
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Solution Overview
Problem
Current IC design optimization tools fail to accurately model resistance and capacitance of routed nets, leading to sub-optimal designs due to significant variations across metal layers, especially in advanced technology nodes, resulting in poor convergence and quality of results.
Innovation Solution
The implementation of an integrated metal layer aware optimization approach that computes accurate resistance and capacitance values, using a layer calibration model to determine optimal metal layers for routing, and updates metal layer utilization dynamically, allowing concurrent metal layer assignment and optimization, thereby improving timing convergence and reducing area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional unit-RC models are used for resistance and capacitance estimation, then the design process is simpler and faster, but the accuracy of timing analysis deteriorates due to significant variations across metal layers
Solution Approach 1:
The patent applies local quality by assigning different resistance and capacitance characteristics to different metal layers. Instead of using a uniform unit-RC model, the system creates layer-specific RC values that reflect the actual physical properties of each metal layer, thereby improving timing analysis accuracy while managing complexity through localized differentiation.
Solution Approach 2:
The patent changes the parameters of the RC model from generic unit values to specific layer-dependent values. By computing resistance and capacitance values that are specific to each metal layer based on routing cost analysis, the system transforms the model from a simplified uniform approach to a differentiated approach that captures actual variations across layers.
2Manufacturing precision
If metal layer assignment is performed after optimization, then the optimization process is simpler, but the quality of results deteriorates due to timing pessimism and constraints
Solution Approach 1:
The patent applies preliminary action by performing metal layer assignment during the optimization process rather than after. This allows the optimizer to make informed decisions about buffer insertion, gate resizing, and net restructuring with knowledge of the actual RC characteristics of different metal layers, eliminating timing pessimism and achieving superior convergence.
Solution Approach 2:
The patent implements feedback by using the computed RC values and routing costs to guide optimization decisions. The system continuously evaluates the impact of design changes on timing and routing metrics, using this feedback to iteratively improve the design quality without introducing excessive complexity.
3Measurement precision
If accurate layer-specific RC values are computed, then timing analysis accuracy improves, but the computational runtime increases
Solution Approach 1:
The patent applies partial action by computing RC values selectively based on routing cost estimates rather than performing exhaustive calculations for all possible layer assignments. The system computes sufficient accuracy to guide optimization decisions without performing excessive computations, thereby balancing precision with runtime efficiency.
4Manufacturing precision
If routing cost is computed based on multiple parameters including metal layer utilization, then the routing decisions are more accurate, but the computational complexity increases
Solution Approach 1:
The patent applies universality by creating a multi-parameter routing cost model that serves multiple functions: estimating RC values, guiding layer assignment, and evaluating optimization decisions. This unified cost function integrates horizontal length, vertical length, pin layers, timing slack, and layer utilization into a single comprehensive metric that simplifies the overall optimization process despite the multiple parameters involved.
Data Source
AI summary
Systems and techniques are described for optimizing an integrated circuit (IC) design. Before routing is performed on the IC design in an IC design flow, an IC design tool can iteratively perform a set of operations, the set of operations comprising: (1) modifying a net in the IC design to obtain a modified net, (2) determining a metal layer for routing the modified net, (3) computing a resistance value and a capacitance value of the modified net based on the metal layer, and (4) computing a delay value for the modified net based on the resistance value and the capacitance value.