Semiconductor Metal Layer Protection for Probe Test Deformation
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Solution Overview
Problem
The deformation of metal layers in semiconductor devices due to probe insertion during electrical testing leads to processing abnormalities, necessitating the omission of electrical tests, which complicates identifying electrical abnormalities post-processing and results in waste of resources.
Innovation Solution
A method involving forming a protective layer on the metal layer to cover the protruded portion, removing the protruded portion, and creating a dielectric layer to cover the exposed surface, followed by forming a conductive plug for electrical lead-out, thereby addressing the deformation issue and enabling subsequent processing without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a probe is inserted into the metal layer to perform electrical testing, then electrical quality can be determined, but the metal layer deforms with a height of 3 micrometers or more
Solution Approach 1:
The patent applies preliminary action by forming a protective layer on the metal layer surface before electrical testing. This protective layer prevents probe insertion from deforming the metal layer, allowing electrical testing to proceed without compromising manufacturing precision. The protective layer is subsequently removed after testing, having served its protective function during the critical testing phase.
Solution Approach 2:
The protective layer acts as an intermediary between the probe and the metal layer. It allows the probe to make contact for electrical testing while preventing direct mechanical interaction that would cause deformation. The intermediary layer transfers the necessary electrical function while isolating the metal layer from harmful mechanical stress.
2Manufacturing precision
If electrical testing is omitted to avoid metal layer deformation, then manufacturing precision is maintained, but electrical abnormalities cannot be identified until after post-processing
Solution Approach 1:
The protective layer enables preliminary electrical testing to be performed before post-processing. By protecting the metal layer during testing, the patent allows quality determination to occur at the optimal time - early in the manufacturing process - rather than forcing a choice between maintaining precision or obtaining electrical data.
Solution Approach 2:
The patent implements feedback by enabling electrical testing results to be obtained and used during the manufacturing process. The protective layer ensures this feedback can be gathered without negative consequences, allowing real or near-real-time quality information to guide subsequent manufacturing decisions and prevent waste of resources on defective devices.
3Productivity
If electrical testing is performed without protective measures, then testing can be conducted, but post-processing operations such as bonding and photolithography are affected by probe marks
Solution Approach 1:
The protective layer serves as a temporary intermediary that enables testing while protecting against harmful effects. It allows the probe to perform its function without creating permanent damage that would interfere with post-processing. After testing completes, the protective layer is removed, having fulfilled its role of preventing probe mark formation during the critical testing phase.
Data Source
AI summary
A manufacturing method for a semiconductor device includes: obtaining a pre-processed semiconductor structure, wherein the pre-processed semiconductor structure comprises a metal layer (103) having a first exposed surface (1032), and the first exposed surface (1032) of the metal layer has a protrusion portion (1031); arranging a protective layer (104) on the first exposed surface (1032) of the metal layer, wherein the protective layer (104) at least covers part of the metal layer (103) that excludes the protrusion portion (1031); removing the protrusion portion (1031) to form on the metal layer (103) a second exposed surface (1033) of the metal layer (103); and forming a dielectric layer (105) on an area where the first exposed surface (1032) is located, wherein the dielectric layer (105) completely covers the area where the first exposed surface (1032) is located.