Metal Layer Structures in Semiconductor Devices

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Solution Overview

Problem

Existing metal line forming techniques in semiconductor devices have a tight process window, leading to the formation of short dummy conductive lines that increase parasitic capacitance and affect device performance.

Innovation Solution

A method involving the formation of L-shaped openings and fill material in a second cut metal etch step to widen the process window and eliminate dummy conductive lines, using a spacer material layer and antireflective coating to define conductive lines without forming short segments that act as dummy lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If existing metal line forming techniques are used, then the process can be completed with standard methods, but the process window remains tight and short dummy conductive lines are formed

Engineering Contradiction:
Improveprocess windowVSAvoiddummy conductive lines formation
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the metal line formation process into multiple distinct steps: forming L-shaped openings in the antireflective coating layer, selectively filling certain openings with conductive material, and removing unfilled portions. This segmentation allows precise control over where conductive material is deposited, eliminating the formation of unwanted dummy lines while widening the process window.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by forming the L-shaped openings and applying the antireflective coating before the actual metal deposition. The antireflective coating is applied in advance to prevent unwanted metal deposition in certain areas, and the L-shaped openings are pre-formed to guide the subsequent selective filling process, ensuring precise metal line formation without dummy lines.

Inventive Principle:
Principle #10Preliminary action

2Object-generated harmful factors

If existing metal line forming techniques are used, then the fabrication process remains simple, but parasitic capacitance increases due to short dummy conductive lines

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidfabrication process complexity
Core Design Contradiction:
Object-generated harmful factorsVSEase of manufacture

Solution Approach 1:

The patent applies local quality by creating L-shaped openings with specific geometries in the antireflective coating layer. These openings have different shapes and locations tailored to the specific requirements of each metal line. By locally modifying the antireflective coating structure, the patent enables selective metal deposition only where needed, eliminating parasitic capacitance from dummy lines while maintaining manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The antireflective coating layer serves as an intermediary element between the substrate and the conductive material. It mediates the metal deposition process by preventing metal from depositing in areas where L-shaped openings are not present, while allowing controlled deposition in areas with openings. This intermediary layer enables precise metal line formation without requiring complex direct patterning methods.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If dummy conductive lines are formed, then the metal layer structure is complete, but device performance deteriorates due to increased parasitic capacitance

Engineering Contradiction:
Improvedevice performanceVSAvoidconductive material deposition
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts or removes the harmful element (dummy conductive lines) from the metal layer structure by using L-shaped openings in the antireflective coating to prevent metal deposition in unwanted areas. Instead of forming complete continuous metal lines everywhere, the method selectively deposits metal only where functional conductive lines are needed, extracting the parasitic capacitance problem from the structure.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter of conductive material deposition by controlling where and how much metal is deposited. Through the L-shaped opening geometry and selective filling process, the method changes the deposition pattern from uniform continuous lines to targeted segmented lines, reducing the total quantity of conductive material in unwanted locations while maintaining necessary connections.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10727113B2Methods of forming metal layer structures in semiconductor devices
Publication Date: 2020.07.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10727113B2 patent drawing
  • US10727113B2 patent drawing
  • US10727113B2 patent drawing

AI summary

A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.