Metal Layer Thickness Layout for Power Device Thermal Stress Relief
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Solution Overview
Problem
Power semiconductor devices face issues with thermal deformations and stresses due to mismatched coefficients of thermal expansion (CTE) between constituent materials, leading to cracks in insulating layers and reduced yield and reliability.
Innovation Solution
A power semiconductor device design featuring a metal layer with a first portion and a second portion, where the second portion is farther from the substrate edge and thicker than the first, along with a protective layer and coating layer to absorb and distribute thermal stresses, reducing tensile stresses and bending moments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform thickness metal layer is used, then the manufacturing process is simple, but thermal stresses are high during thermal processes
Solution Approach 1:
The metal layer is designed with non-uniform thickness, where the first portion has a first thickness and the second portion has a second thickness different from the first thickness. This local variation in thickness allows different regions of the metal layer to have different mechanical properties, specifically reducing thermal stress concentration in critical areas during thermal processes while maintaining manufacturing feasibility through standard deposition techniques with selective etching or deposition control.
2Adaptability or versatility
If materials with different CTEs are used in the packaged structure, then functional requirements are met, but thermal deformations and stresses increase
Solution Approach 1:
The invention addresses CTE mismatch by changing the geometric parameter of the metal layer (thickness distribution) rather than changing material properties. The non-uniform thickness profile compensates for the thermal expansion differences between materials with different CTEs, allowing the structure to accommodate thermal deformations without generating excessive stresses that would compromise structural stability.
3Area of stationary object
If the metal layer extends to the substrate edge, then the device area is maximized, but tensile stresses cause cracks in insulating layers
Solution Approach 1:
The metal layer is designed with spatially varying thickness, where the thickness distribution is optimized to reduce tensile stress at critical locations near the substrate edge. This allows the metal layer to extend closer to the substrate edge, maximizing device area, while the reduced thickness in stress-prone regions prevents crack formation in the insulating layers by lowering the stress concentration factor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively minimizes thermal stresses and prevents cracks in insulating layers, enhancing the device's integrity and reliability by distributing stresses through elastic energy absorption and using materials with similar CTEs.
Implementation Method 1
Mismatch of coefficient of thermal expansion (CTE) between constituent materials of the packaged structure may induce thermal deformations and stresses
Implementation Method 2
stresses exerted on the first portion during a thermal process
Data Source
AI summary
A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.