Metal Layer Tip-to-Tip Short Prevention via Trench Silicide Cut
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Solution Overview
Problem
The challenge in integrated circuit fabrication is achieving precise alignment and separation of metal layers during the back-end of line (BEOL) process, particularly with optical lithography, which often results in misalignment and inadequate tip-to-tip spacing in metal layer processing.
Innovation Solution
A novel trench silicide (TS) cut process is introduced, which involves forming trench contacts on source and drain regions, filling them with a dielectric material, and patterning metal layers such that their tips are self-aligned to the filling material, eliminating dependence on lithography for tip-to-tip alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If optical lithography is used for metal layer patterning, then device complexity and integration are improved, but manufacturing precision of metal tip-to-tip spacing deteriorates due to misalignment
Solution Approach 1:
The patent introduces an intermediary alignment mark structure formed in the interlayer dielectric that serves as a reference for self-aligning metal layer tips. This intermediary structure mediates between the lithography process and the final metal spacing, eliminating direct dependence on lithography alignment while enabling precise tip-to-tip spacing through the alignment mark geometry
Solution Approach 2:
The alignment mark structure is formed preliminarily in the interlayer dielectric before metal layer deposition. This preliminary action establishes the spacing reference in advance, allowing subsequent metal layers to be self-aligned to these pre-formed marks, thereby ensuring precise tip-to-tip spacing independent of lithography alignment variations
2Productivity
If tighter metal tip-to-tip spacing is achieved to increase density, then productivity is improved, but reliability deteriorates due to increased risk of shorts and process variability
Solution Approach 1:
The metal layer tips are designed to self-align to the alignment marks through the patterning process, eliminating the need for complex lithography alignment steps. This self-service mechanism ensures consistent spacing and reduces process variability, maintaining reliability even at tighter pitch
Solution Approach 2:
The patent moves the alignment reference from the planar lithography dimension to the vertical dimension by forming alignment marks that extend through the interlayer dielectric. This dimensional transition allows spacing control to be determined by the height and geometry of the alignment marks rather than by lateral lithography precision, enabling tighter spacing with maintained reliability
Data Source
AI summary
Techniques relate to forming an integrated circuit. Trench contacts are formed on top of at least one source and drain of an intermediate structure. An interlayer dielectric is formed on top of the intermediate structure. A trench is cut through the interlayer dielectric, through at least one of the trench contacts, down to a shallow trench isolation area. The trench is filled with a filling material. Upper contacts are formed on top of the trench contacts in the interlayer dielectric. A first metal layer pattern is patterned such that a separation is formed by a filling material width of the filling material. First metal layers are formed according to the first metal layer pattern, where tips of the first metal layers are aligned to the filling material that fills the trench, such that the tips of the first metal layers are separated by the filling material width.