Metal Line Resistivity Reduction via Grain Growth and Annealing
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Solution Overview
Problem
Conventional damascene processing and subtractive metal etching techniques face challenges in forming interconnects with small feature sizes, leading to increased resistivity due to line edge roughness, grain size issues, and impurities, which affect the performance of integrated circuits (ICs).
Innovation Solution
The method involves depositing a first metal layer atop a second metal layer to increase grain size, etching to form a metal line, removing impurities through hydrogen treatment, and annealing at pressures between 760 Torr and 76,000 Torr to reduce line edge roughness and improve resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional damascene processing is used to form metal interconnects, then the process is compatible with existing manufacturing, but the liner/seed coverage is poor and reentrant profiles occur leading to voids and defects
Solution Approach 1:
The patent inverts the conventional damascene approach by using subtractive etching of a continuous metal layer instead of additive filling of openings. This reverses the process logic to avoid liner coverage issues and reentrant profiles entirely, as the metal is removed rather than deposited in confined spaces
Solution Approach 2:
The patent extracts the problematic liner/seed layer from the process by using a continuous metal layer that is etched back. This eliminates the interface between liner and metal that causes adhesion problems and void formation, directly addressing the reliability issue
2Length of moving object
If metal line width is reduced to achieve smaller feature sizes, then IC scaling is enabled, but resistivity increases due to surface scattering and grain boundary effects
Solution Approach 1:
The patent changes the physical parameters of the metal layer by controlling grain size through deposition conditions and applying thermal annealing. This modifies the electrical properties to reduce surface scattering effects, thereby lowering resistivity in narrow lines while maintaining scalability
Solution Approach 2:
The patent performs preliminary grain growth and impurity removal through annealing before the metal layer is etched to form final interconnects. This pre-treatment ensures optimal electrical properties are established before the metal is patterned into narrow lines
3Reliability
If subtractive metal etching is used to increase conductor volume, then resistivity is lowered, but line edge roughness increases due to grain size and impurities
Solution Approach 1:
The patent performs preliminary annealing treatments before etching to grow larger grains and remove impurities from the metal layer. This pre-treatment reduces the sources of line edge roughness before the subtractive etching process occurs
Solution Approach 2:
The patent replaces mechanical/physical grain refinement methods with thermal annealing processes that use heat to control grain growth and impurity distribution, providing better control over line edge quality in the subtractive etching process
4Ease of manufacture
If impurities are present in the metal layer, then deposition is simpler, but resistivity and line edge roughness increase
Solution Approach 1:
The patent performs preliminary cleaning and annealing treatments after deposition but before etching to remove impurities. This maintains the simplicity of the deposition process while adding a subsequent purification step to achieve low resistivity
Solution Approach 2:
The patent introduces thermal annealing as an intermediary process between deposition and etching. This intermediate treatment removes impurities and optimizes grain structure without requiring changes to the deposition or etching processes themselves
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers the resistivity of metal lines, reduces line edge roughness, and enhances IC performance by maximizing conductor volume and material flexibility.
Implementation Method 1
depositing a first metal layer atop a second metal layer under conditions sufficient to increase a grain size of a metal of the first metal layer
Implementation Method 2
removing impurities from the metal line by a hydrogen treatment process
Implementation Method 3
annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness
Data Source
AI summary
Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.