Metal Line Patterning With Self-Aligned Spacers for Sub-50 Nm Gaps
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Solution Overview
Problem
Current lithography techniques face challenges in reliably patterning metal lines with small line-end distances due to exposure limitations, leading to increased complexity and cost in semiconductor manufacturing, especially when line-end distances are below 50 nm.
Innovation Solution
A self-aligned double patterning technique is employed, involving the formation of mandrel layers, spacer layers, and filling features, with multiple patterning processes to achieve metal lines with varying line-end distances in a single exposure, reducing the need for additional lithography-etching processes and controlling line widths accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lithography techniques are used to pattern metal lines with small line-end distances, then manufacturing process simplicity is maintained, but patterning reliability deteriorates when line-end distances are below 50 nm
Solution Approach 1:
The patent divides the single patterning process into multiple sequential patterning steps: forming mandrels, depositing spacers, removing mandrels, and forming additional structures. This segmentation allows each step to be optimized independently, achieving reliable patterning of metal lines with small line-end distances below 50 nm while maintaining overall process control
Solution Approach 2:
The patent performs preliminary actions by forming mandrels and spacers before final metal line patterning. The mandrels are formed first, then spacers are deposited on mandrel sidewalls, and mandrels are removed to create precise patterns. This preliminary structuring enables accurate control of line-end distances that would be impossible with direct conventional lithography
2Manufacturing precision
If additional lithography-etching processes are used to achieve precise line-end distances, then manufacturing precision is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent employs self-aligned patterning where spacers automatically form on mandrel sidewalls with precise alignment, eliminating the need for separate alignment steps. The mandrel structures serve their own purpose as alignment references for spacer formation, and the spacer width is self-determined by deposition thickness control. This self-service mechanism achieves sub-50 nm line-end distance precision without adding complex alignment procedures
Solution Approach 2:
The patent controls line-end distance precision by changing physical parameters: spacer deposition thickness controls line width, mandrel spacing controls line-end distances, and etch selectivity parameters enable precise pattern transfer. By adjusting these parameters, the process achieves high manufacturing precision for metal lines with varying line-end distances without requiring multiple lithography tools
3Manufacturing precision
If dummy metal lines are added to control line widths, then manufacturing precision is improved, but RC delays increase and layout flexibility is reduced
Solution Approach 1:
The patent uses spacer structures that self-align to mandrels to define metal line widths, eliminating the need for dummy metal lines. The spacer width, controlled by deposition thickness, directly determines the metal line width through pattern transfer. This self-service approach provides precise line width control without adding extra metal structures that would increase RC delays
Solution Approach 2:
The patent extracts the line width control function from metal line structures themselves and transfers it to spacer structures. Instead of using dummy metal lines to control widths, the process separates the control function (spacers) from the functional metal lines, allowing precise width definition without adding harmful dummy structures to the electrical network
Data Source
AI summary
A method for metal patterning is provided. A plurality of mandrel recesses are formed in a mandrel layer over a semiconductor substrate. A plurality of spacers are formed respectively in the mandrel recesses. Each of the spacers is connected to a sidewall of the corresponding one of the mandrel recesses and has a spacer recess formed therein. A plurality of filling features are formed respectively in the spacer recesses. A first patterning process is performed to pattern the mandrel layer to form a first line pattern. A second patterning process is performed to pattern the filling features to form a second line pattern. A plurality of metal lines are formed in the semiconductor substrate, and are arranged in a pattern that is a combination of the first line pattern and the second line pattern.