Metal Line Spacer Patterning for Tighter Via-to-Via Spacing

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Solution Overview

Problem

Existing semiconductor manufacturing techniques face challenges in reducing via-to-via spacing without the need for additional masking layers, leading to increased complexity, cost, and limitations in achieving necessary design rules for compact chip design.

Innovation Solution

Employing double-patterning techniques that create an hour-glass pattern in the litho stack, deposit a spacer assuming this shape, and etch the litho stack to expose metal lines with sharp distal ends, reducing the distance between metal lines without an additional masking layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional single patterning is used, then manufacturing process is simple, but via-to-via spacing cannot be reduced below lithographic limits

Engineering Contradiction:
Improvevia-to-via spacingVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patterning process is divided into two separate steps: first forming mandrels with initial pattern, then depositing spacers to create the final pattern. This segmentation allows each step to work within standard lithographic capabilities while achieving sub-lithographic feature spacing through the combined effect of mandrels and spacers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The mandrel structure serves as an intermediary element that enables spacer deposition at non-90 degree angles. The mandrel is not part of the final device but facilitates the creation of the desired metal line pattern through spacer formation, then gets removed. This intermediary approach allows precise spacing control without additional lithographic steps.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If additional masking layers are added to reduce spacing, then via-to-via spacing is reduced, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvevia-to-via spacingVSAvoidmanufacturing process simplicity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

Instead of adding more lithographic layers (2D complexity), the solution transitions to utilizing the vertical dimension through angled spacer deposition. The spacer is deposited at a non-90 degree angle relative to the mandrel, creating precise lateral spacing through controlled vertical-to-lateral geometry conversion, thereby avoiding additional masking steps.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The deposition angle parameter is changed from the conventional 90 degrees to a specific non-90 degree angle. This parameter change in the spacer deposition process enables the spacer to self-align and define precise via-to-via spacing without requiring additional photomask layers, thus maintaining manufacturing simplicity while achieving reduced spacing.

Inventive Principle:
Principle #35Parameter changes

3Area of stationary object

If via-to-via spacing is reduced for compact design, then chip area is reduced, but electrical isolation between adjacent metal lines becomes challenging

Engineering Contradiction:
Improvechip areaVSAvoidelectrical isolation
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The spacer is deposited preliminarily to establish electrical isolation between metal lines before the metal lines themselves are formed. By pre-positioning the dielectric spacer at the precise location where metal lines will be deposited, the structure ensures that even when metal lines are placed closer together, they remain electrically isolated by the pre-formed spacer barrier.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Achieves denser active via spacing by defining minimum via-to-via and via-to-rail spacing through a merged spacer deposition process, reducing the need for additional masking levels and enhancing reliability and design compactness.

Implementation Method 1

depositing a spacer assuming an hour-glass pattern shape

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

depositing a spacer assuming an hour-glass pattern shape

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

etching the litho stack to expose the mandrel layer and metal lines

Methodology Applied
Scientific EffectReactive Ion Etching: Plasma

Data Source

PatentUS12400871B2Metal lines with low via-to-via spacing
Publication Date: 2025.08.26 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12400871B2 patent drawing
  • US12400871B2 patent drawing
  • US12400871B2 patent drawing

AI summary

A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.