Metal Liner Overhang Reduction in Semiconductor Trenches

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Solution Overview

Problem

The challenge in semiconductor manufacturing is filling small openings or trenches with conductive materials due to overhang issues during the fabrication process, leading to voids and increased contact resistance in conductive features.

Innovation Solution

An etching process using a halide of the metal in the seed or liner layer is employed to remove or reduce overhangs, allowing for the complete filling of openings with conductive layers without voids by forming a self-limiting etching process that reacts with the metal without affecting the underlying or oxidized layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conductive materials are deposited to fill small openings or trenches, then the openings can be filled with conductive features, but overhang issues occur leading to voids and increased contact resistance

Engineering Contradiction:
Improvefilling completenessVSAvoidelectrical connection reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

An etching process is performed before the conductive material deposition to remove overhangs from the opening walls. This preliminary action prevents the overhangs from interfering with subsequent complete filling, eliminating void formation and ensuring reliable electrical connections.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The harmful overhang structures are selectively removed from the opening walls before filling. By extracting these problematic features that would otherwise prevent complete filling, the process enables void-free conductive feature formation and maintains electrical connection reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If feature sizes are scaled down to increase functional density, then production efficiency increases and costs decrease, but filling small openings becomes more difficult

Engineering Contradiction:
Improveproduction efficiencyVSAvoidfilling difficulty
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The etching step is introduced as a preliminary process before deposition to prepare the opening walls by removing overhangs. This enables successful filling of scaled-down features while maintaining high production efficiency, as the additional step is simple and does not significantly increase process complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The process introduces a new parameter (etching treatment) that changes the surface morphology of the opening walls. By modifying the wall profile to remove overhangs, the filling process becomes feasible even for very small scaled-down features, maintaining ease of manufacture despite size reduction.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures reliable electrical connections by eliminating voids in conductive features, reducing resistance, and improving the reliability of semiconductor devices by ensuring the conductive layers fill the openings without gaps.

Implementation Method 1

An etching process using a halide of the metal in the seed or liner layer is employed to remove or reduce overhangs

Methodology Applied
Scientific EffectChemical etching: Chemical Bonding

Data Source

PatentUS9899258B1Metal liner overhang reduction and manufacturing method thereof
Publication Date: 2018.02.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9899258B1 patent drawing
  • US9899258B1 patent drawing
  • US9899258B1 patent drawing

AI summary

Overhang reduction methods are disclosed. In some embodiments, a method includes forming a recess in a dielectric layer, the recess defining first sidewalls of the dielectric layer. The method also includes depositing a first conductive layer over an upper surface of the dielectric layer and the sidewalls of the dielectric layer, the first conductive layer having a first overhang, removing the first overhang of the first conductive layer using an etchant selected from the group consisting of a halide of the first conductive layer, Cl2, BCl3, SPM, SC1, SC2, and combinations thereof, and filling the recess with a second conductive layer.