Metal Nanoparticle Floating Gates for Vertical Memory Cell Speed
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Solution Overview
Problem
Current three-dimensional memory device fabrication techniques do not effectively enhance memory performance despite increasing memory density through vertical cell string formation, as they rely on traditional materials and processes that limit bandwidth and performance.
Innovation Solution
Incorporating metal nano-particles into the floating gates of memory cells, either on the surface or infused into the polysilicon material, to improve charge storage and programming/erase speed, while using advanced fabrication techniques like atomic layer deposition and chemical mechanical planarization to optimize the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional polysilicon materials are used in vertical memory cell strings, then manufacturing simplicity is maintained, but programming and erase speed are limited
Solution Approach 1:
The patent combines metal nanoparticles with polysilicon to form a composite floating gate structure. The metal nanoparticles (such as tungsten, platinum, or aluminum) are embedded within the polysilicon matrix, creating a composite material that leverages the charge storage capabilities of polysilicon while adding the high conductivity and fast charge transfer properties of metal particles, thereby improving programming and erase speed
Solution Approach 2:
The patent introduces metal nanoparticles at specific locations within the floating gate structure, particularly at the interface between the tunnel oxide and the polysilicon, or distributed throughout the polysilicon volume. This localized enhancement of charge storage and charge transfer properties at critical regions improves performance without requiring complete restructuring of the entire memory cell
2Quantity of substance
If vertical three-dimensional structures are used, then memory density is increased, but memory performance and bandwidth are not effectively enhanced
Solution Approach 1:
By incorporating metal nanoparticles into the vertical memory cell structure, the patent enhances the charge storage and charge transfer capabilities of each individual cell. The metal particles provide rapid charge injection and extraction pathways, enabling faster programming and erasing operations in the three-dimensional vertical architecture, thus improving overall memory bandwidth and performance while maintaining high density
3Reliability
If metal nanoparticles are added to floating gates, then charge storage and programming speed are improved, but risk of floating gate shorting increases
Solution Approach 1:
The patent carefully controls the distribution and concentration of metal nanoparticles within the floating gate, placing them primarily at the tunnel oxide-poly silicon interface or in specific regions away from direct contact points. This localized placement maximizes charge storage effectiveness while minimizing the probability of conductive pathways forming between adjacent floating gates
Solution Approach 2:
The patent utilizes the porous or distributed nature of metal nanoparticle incorporation, where discrete particles are separated by insulating polysilicon matrix and tunnel oxide layers. This structure allows efficient charge transfer to individual particles while the surrounding insulating materials prevent direct electrical contact between particles in adjacent cells, reducing shorting risk
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory performance by improving programming and erase speed, maintaining high memory density, and preventing floating gate shorting, thus addressing the limitations of traditional methods.
Implementation Method 1
using advanced fabrication techniques like atomic layer deposition and chemical mechanical planarization to optimize the structure
Data Source
AI summary
A method for forming a string of memory cells, a memory device having a string of memory cells, and a system are disclosed. The string of memory cells can include a string of planar memory cells formed as recesses in each of a plurality of control gate material formed as a vertical stack of alternating insulator and control gate material. The recesses can be lined with a dielectric material and filled with a floating gate material. Metal nano-particles can be formed on a surface of the floating gate material and/or infused into the floating gate material.