Metal Nitride Gate Etching Damage Reduction

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Solution Overview

Problem

Conventional etching processes for forming gate electrodes in semiconductor transistors often cause damage to the gate insulating layer and semiconductor substrate, leading to deterioration in electrical characteristics, and require additional unit processes to mitigate this damage, increasing fabrication costs.

Innovation Solution

The method involves forming a gate insulating layer and a metal nitride layer on a semiconductor substrate, using a mask pattern as an etching mask and the gate insulating layer as an etching buffer to perform an etching process on the metal nitride layer, with an etchant containing an oxidizing agent, chelate agent, and pH adjusting mixture to reduce etching damage, and forming a metal nitride layer pattern.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a plasma etchant is used to etch the metal nitride layer, then the etching process can be performed, but etching damage occurs to the gate insulating layer and semiconductor substrate

Engineering Contradiction:
Improveetching process efficiencyVSAvoidetching damage to gate insulating layer and substrate
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary protective layer (silicon oxide or silicon nitride) between the plasma etchant and the gate insulating layer/substrate. This intermediary layer absorbs the harmful plasma effects while allowing the etching process to proceed on the metal nitride layer, thus resolving the contradiction between etching efficiency and damage prevention

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective layer is formed beforehand before the plasma etching process to cushion and absorb the harmful effects of plasma on the gate insulating layer and substrate. This prior cushioning prevents damage before it occurs, enabling safe plasma etching of the metal nitride layer

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Object-affected harmful factors

If additional unit processes are added to reduce plasma damage, then damage to the gate insulating layer and substrate is reduced, but fabrication cost increases

Engineering Contradiction:
Improveplasma damage reductionVSAvoidnumber of processing steps
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The protective layer formation is merged with the existing gate electrode fabrication process sequence. The protective layer is formed as part of the standard process flow before etching, combining the damage protection function with the existing manufacturing steps rather than adding separate corrective processes afterward

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces etching damage to the gate insulating layer and semiconductor substrate, improving the electrical characteristics of the transistor while minimizing additional processing steps and costs.

Implementation Method 1

an etchant containing an oxidizing agent, chelate agent, and pH adjusting mixture

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

an etchant containing an oxidizing agent, chelate agent, and pH adjusting mixture

Methodology Applied
Scientific EffectChelation:

Data Source

PatentUS8637942B2Transistor having a metal nitride layer pattern, etchant and methods of forming the same
Publication Date: 2014.01.28 SAMSUNG ELECTRONICS CO LTD
  • US8637942B2 patent drawing
  • US8637942B2 patent drawing
  • US8637942B2 patent drawing

AI summary

A transistor having a metal nitride layer pattern, etchant and methods of forming the same is provided. A gate insulating layer and/or a metal nitride layer may be formed on a semiconductor substrate. A mask layer may be formed on the metal nitride layer. Using the mask layer as an etching mask, an etching process may be performed on the metal nitride layer, forming the metal nitride layer pattern. An etchant, which may have an oxidizing agent, a chelate agent and/or a pH adjusting mixture, may perform the etching. The methods may reduce etching damage to a gate insulating layer under the metal nitride layer pattern during the formation of a transistor.