Metal Oxide Fin Access Transistor for High-Density Memory Cells
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Solution Overview
Problem
As semiconductor devices scale to smaller dimensions, integrating access transistors capable of handling sufficient electrical current into the limited area of a semiconductor die becomes increasingly difficult.
Innovation Solution
The integration of a semiconducting metal oxide fin transistor as an access transistor in a memory cell, utilizing a series connection between a bit line and a source line, with a gate electrode controlling the switching of the transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistors are used in memory cells, then the transistor can control electrical current through the memory cell, but the transistor occupies excessive die area preventing high-density integration
Solution Approach 1:
The transistor is transformed from a planar structure to a three-dimensional FinFET structure with a vertical fin extending from the substrate. The gate electrode wraps around the fin in a FinFET configuration, utilizing the vertical dimension to increase the effective channel area without proportionally increasing the planar footprint. This dimensional transition allows the transistor to maintain sufficient current handling capability while reducing the area occupied on the semiconductor die.
2Productivity
If transistor size is reduced to increase device density, then more devices can be integrated into limited die area, but the transistor becomes incapable of handling sufficient electrical current
Solution Approach 1:
By transitioning to a vertical FinFET structure, the effective channel area is increased through the vertical fin height without increasing the planar footprint. This allows the transistor to handle sufficient electrical current even when the planar dimensions are scaled down for high-density integration.
Solution Approach 2:
The transistor employs a composite structure combining the vertical fin region with the wrapped gate electrode. The fin provides the current-conducting channel while the gate electrode provides control, creating a composite structure that optimizes both current handling capability and area efficiency.
3Productivity
If access transistor area is reduced for high-density packing, then more memory cells can be integrated, but the transistor switching control becomes insufficient
Solution Approach 1:
The vertical FinFET structure increases the effective gate control area through the vertical fin, providing sufficient switching control capability even when the planar transistor footprint is reduced for high-density memory cell integration.
Solution Approach 2:
The composite structure of the vertical fin and wrapped gate electrode creates an efficient control mechanism where the gate electrode provides robust switching control despite the reduced planar area, ensuring reliable transistor operation in high-density memory arrays.
Data Source
AI summary
A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.