Metal Oxide Fin Access Transistor for High-Density Memory Current
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Solution Overview
Problem
As semiconductor devices scale to smaller dimensions, integrating access transistors capable of handling sufficient electrical current into the limited area of a semiconductor die becomes increasingly difficult, posing a challenge for memory cell functionality.
Innovation Solution
The integration of a semiconducting metal oxide fin transistor as an access transistor in a back-end-of-line metal wiring level, with a series connection between the access transistor and the memory cell, utilizing field effect transistors on a single crystalline semiconductor layer to efficiently control electrical current and enable high-density device packing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled to smaller dimensions, then device density is improved, but the ability to integrate access transistors capable of handling sufficient electrical current deteriorates
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures, utilizing vertical channel formation to increase the effective channel area without increasing the lateral footprint. This dimensional change allows sufficient current handling capability to be maintained even as device dimensions are scaled down, resolving the contradiction between device density and electrical current handling capability.
Solution Approach 2:
The FinFET structure embeds multiple channel surfaces within a compact vertical footprint, effectively nesting the channel conduction paths within the fin structure. This allows the transistor to handle sufficient electrical current through multiple exposed channel surfaces while occupying minimal die area, thereby improving device density without sacrificing current handling capability.
2Productivity
If access transistors are integrated into limited die area, then device density is improved, but the electrical current handling capability deteriorates
Solution Approach 1:
By forming vertical fins with exposed channel surfaces on multiple sides, the patent increases the effective channel width within a limited lateral footprint. This dimensional transition allows the access transistor to maintain sufficient electrical current handling capability while occupying reduced die area, thus improving device density without compromising power delivery capability.
Solution Approach 2:
The FinFET structure concentrates the channel conduction capability at the fin edges where the channel is thinnest, creating locally optimized current paths. This local quality enhancement allows sufficient electrical current to be handled through the vertical fin structure while minimizing the overall device footprint, thereby achieving high device density without sacrificing current handling capability.
Data Source
AI summary
A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.