Vertically Stacked GAA CFET Using Metal Oxide Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, which affects production efficiency and cost.
Innovation Solution
The implementation of a gate-all-around (GAA) transistor structure with a complementary FET (CFET) configuration, where a first transistor with semiconductor channel layers is vertically stacked with a second transistor featuring metal oxide channel layers, allowing for improved mobility and reduced lattice mismatch, enabling more efficient and cost-effective manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically stacked GAA transistor structures. This dimensional change allows functional density to increase without proportionally increasing fabrication complexity, as the vertical stacking enables multiple devices to occupy the same footprint area while using adapted but manageable processing steps.
Solution Approach 2:
The invention divides the transistor structure into multiple discrete layers including channel layers, sacrificial layers, gate structures, and source/drain structures stacked vertically. This segmentation allows each layer to be formed using separate, well-defined fabrication steps, making the overall complex structure achievable through modular processing rather than requiring monolithic complex operations.
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but manufacturing reliability deteriorates
Solution Approach 1:
The patent employs parameter changes by transitioning from conventional silicon channel materials to metal oxide semiconductor materials for the channel layers. This material parameter change enables formation of reliable nanoscale channels with controlled electrical properties, maintaining device reliability even as feature sizes decrease. The metal oxide materials provide stable threshold voltages and reduced leakage currents critical for small-scale device reliability.
3Ease of manufacture
If conventional planar transistor structures are used, then fabrication processes are simpler, but device performance and mobility are limited
Solution Approach 1:
The patent implements gate-all-around structures where the gate electrode completely surrounds the channel in three dimensions, providing superior electrostatic control compared to planar gates. This dimensional advancement delivers enhanced device performance and mobility through improved electric field control, while the vertical stacking approach keeps fabrication complexity manageable through layered processing.
Solution Approach 2:
The invention uses composite material structures combining metal oxide semiconductor channels with dielectric gate insulators and conductive gate electrodes. This composite approach optimizes each layer's properties for its specific function, achieving high-performance devices with controlled electrical characteristics that exceed conventional single-material transistor structures.
Data Source
AI summary
A semiconductor device includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor includes a semiconductor channel layer, a first gate structure wrapping around the semiconductor channel layer, and first source/drain structures on opposite ends of the semiconductor channel layer. The second transistor includes a metal oxide channel layer, a second gate structure wrapping around the metal oxide channel layer, and second source/drain structures on opposite ends of the metal oxide channel layer.