Metal Oxide Interlayer Gate Stack for NC-FET Leakage Control
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Solution Overview
Problem
Negative capacitance (NC) transistors face issues with gate current leakage and interface problems, which affect device performance and NC matching, especially in pFETs with ferroelectric interfaces.
Innovation Solution
A metal oxide interlayer structure is introduced, with an interfacial layer thickness of approximately 5-8 Å, to address gate current leakage and interface issues in NC-FETs. This structure includes a first metal oxide layer over the interfacial layer, a ferroelectric layer, and a second metal oxide layer, with selective removal of layers to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker interfacial layer is used to address gate current leakage, then gate current leakage is reduced, but device performance degrades due to large effective oxide thickness
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a thin interfacial layer (5-8 Å) for electrical performance, metal oxide layers for interface stabilization, and a ferroelectric layer for negative capacitance. This segmentation allows each layer to be optimized independently, with the thin interfacial layer preventing gate leakage while the other layers compensate for interface issues without increasing effective oxide thickness.
Solution Approach 2:
The gate structure uses a composite material system combining silicon dioxide (interfacial layer), metal oxides (such as HfO2, Al2O3, Ta2O5), and ferroelectric materials (such as HfZrO4). This composite structure provides both the electrical insulation needed to prevent gate leakage and the ferroelectric properties needed for negative capacitance, while maintaining thin effective oxide thickness through the synergistic combination of materials.
2Reliability
If ferroelectric interface issues are present in pFET, then NC-FET performance is reduced, but adding more interface layers increases device complexity
Solution Approach 1:
The patent applies different material compositions and thicknesses at different interfaces within the gate structure. The interfacial layer has specific thickness (5-8 Å) optimized for electrical performance, while metal oxide layers are positioned specifically at interfaces where they provide stabilization. This local optimization of material properties at critical interfaces improves NC matching without uniformly increasing complexity throughout the entire device structure.
Data Source
AI summary
The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.