Metal Oxide Interlayer for NC nFET/pFET Gate Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Negative capacitance (NC) transistors face issues with gate current leakage and interface problems, which affect device performance and matching, particularly in pFETs due to ferroelectric interface issues and thick effective oxide thickness.
Innovation Solution
A metal oxide interlayer structure is introduced with a thickness of approximately 5-8 Å, comprising an interfacial layer, a first metal oxide layer, a ferroelectric layer, and a second metal oxide layer, optimized to reduce gate current leakage and improve device performance by adjusting the effective oxide thickness and inversion thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker interfacial layer is used to address gate current leakage, then gate current leakage is reduced, but device performance degrades due to large effective oxide thickness
Solution Approach 1:
The gate structure is segmented into multiple distinct layers: an interfacial layer (5-8 Å) for leakage control, and a separate ferroelectric layer for capacitance function. This segmentation allows each layer to be optimized independently - the thin interfacial layer minimizes leakage without significantly increasing effective oxide thickness, while the ferroelectric layer provides the desired negative capacitance effect.
Solution Approach 2:
The interfacial layer acts as an intermediary between the semiconductor substrate and the ferroelectric layer. It provides a controlled interface that reduces gate current leakage while maintaining compatibility between the substrate and ferroelectric material, enabling the ferroelectric layer to function effectively without being compromised by interface defects.
2Use of energy by stationary object
If ferroelectric material is added to lower supply voltage and reduce power consumption, then power consumption is reduced, but gate current leakage increases breaking NC behavior
Solution Approach 1:
The interfacial layer serves as a protective intermediary between the semiconductor substrate and the ferroelectric layer. This thin layer (5-8 Å) passivates interface states that would otherwise cause leakage currents, allowing the ferroelectric material to maintain its negative capacitance behavior without excessive gate leakage.
Solution Approach 2:
The interfacial layer thickness is precisely controlled within a narrow range (5-8 Å) to optimize the balance between leakage reduction and capacitance preservation. This precise parameter control ensures the interface provides sufficient protection against leakage while maintaining the ferroelectric layer's electrical characteristics.
3Reliability
If ferroelectric interface issues are present, then NC matching deteriorates, but device performance is affected
Solution Approach 1:
The interfacial layer provides localized quality improvement at the critical substrate-ferroelectric interface. By concentrating the interface engineering effort in this specific region, the layer improves NC matching and reduces leakage without requiring changes to the bulk properties of the ferroelectric material or the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The metal oxide interlayer structure effectively reduces gate current leakage and improves NC matching and device performance for both nFET and pFET, enhancing the overall performance of NC transistors.
Implementation Method 1
a thickness of the interfacial layer is about 5-8 Å
Implementation Method 2
Gate current leakage issues can be addressed with a thicker interfacial layer
Implementation Method 3
NC transistors add a ferroelectric material layer to conventional transistors to lower required supply voltage and reduce power consumption
Data Source
AI summary
The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.