Metal Oxide Semiconductor Layer Segmentation for 3D NAND Memory
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Solution Overview
Problem
Forming separate channel formation and low-resistance regions in three-dimensional NAND memory using metal oxide semiconductor layers is challenging, requiring precise control to maintain carrier concentration and prevent diffusion of impurities.
Innovation Solution
A semiconductor device structure incorporating a columnar conductor and insulator layers, with a material layer comprising indium, aluminum, gallium, tin, titanium, or zinc oxides, to form distinct channel and low-resistance regions, and using barrier and tunnel insulating films to inhibit oxygen diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If separate channel formation region and low-resistance region are formed in metal oxide semiconductor layer, then data capacity is increased, but manufacturing precision becomes difficult to control
Solution Approach 1:
The metal oxide semiconductor layer is divided into a channel formation region with lower carrier concentration and a low-resistance region with higher carrier concentration. This segmentation allows independent optimization of each region's electrical characteristics while maintaining overall device functionality and increasing data capacity through precise spatial control of carrier concentrations.
Solution Approach 2:
Different regions of the metal oxide semiconductor layer are assigned different carrier concentration characteristics. The channel formation region has lower carrier concentration for high impedance, while the low-resistance region has higher carrier concentration for low impedance. This local quality differentiation enables precise control of electrical properties in specific areas without compromising the entire structure.
2Reliability
If high barrier film is formed in channel formation region to prevent impurity diffusion, then reliability is improved, but device complexity increases
Solution Approach 1:
An insulator layer with appropriate barrier properties is introduced between the channel formation region and the low-resistance region. This intermediary layer prevents impurity diffusion from the low-resistance region into the channel formation region, maintaining carrier concentration stability and device reliability without requiring complex multi-layer structures.
3Productivity
If channel formation region and low-resistance region are made small to increase cell density, then productivity is improved, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The differentiation between channel formation region and low-resistance region is achieved through vertical stacking with distinct insulator layers, allowing precise control of region boundaries in the vertical dimension while maintaining small footprints in the horizontal dimension. This enables high cell density without compromising manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the formation of reliable semiconductor devices with high data capacity by maintaining the integrity of the channel and low-resistance regions, thereby enhancing the performance and reliability of three-dimensional NAND memory.
Implementation Method 1
the second insulator functions as a barrier insulating film that inhibits diffusion of oxygen into the second conductor
Implementation Method 2
the fourth insulator functions as a tunnel insulating film
Implementation Method 3
the sixth insulator functions as a charge accumulation layer
Data Source
AI summary
A semiconductor device with high storage capacity is provided. The semiconductor device includes first to sixth insulators, first to third conductors, and first to third material layers. The first conductor overlaps with a first insulator and a first material layer. A first region of the first material layer overlaps with a second material layer, a second conductor, a second insulator, and a third insulator. The third material layer is positioned in a region including a second region of the first material layer and top surfaces of the second material layer, the second conductor, the second insulator, and the third insulator; a fourth insulator is positioned over the third material layer; the sixth insulator is positioned over the fourth insulator; and a fifth insulator is positioned over the sixth insulator. The third conductor is positioned over the fifth insulator overlapping with the second region of the first material layer. The first to third material layers include oxide containing indium, an element M (M is aluminum, gallium, tin, or titanium), and zinc.