Metal Oxide TFT Threshold Tuning in CMOS-Integrated Interconnects

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Solution Overview

Problem

The integration of thin-film transistors (TFTs) with metal-oxide-semiconductor field-effect transistors (MOSFETs poses challenges in tuning the threshold voltage due to decreased feature sizes, making it difficult to improve device performance effectively.

Innovation Solution

A semiconductor fabrication method involving the formation of multiple gate structures with varying metal oxide features and threshold voltages is developed, where the lattice structure of metal oxide features with different oxygen vacancies are used to achieve distinct conductivity levels, allowing for the tuning of threshold voltages through implantation and annealing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If feature sizes are decreased to scale down MOSFETs, then device integration density is improved, but the ability to tune threshold voltage of TFTs is worsened

Engineering Contradiction:
Improvedevice integration densityVSAvoidthreshold voltage tuning capability
Core Design Contradiction:
Area of moving objectVSAdaptability or versatility

Solution Approach 1:

The patent applies local quality by forming different metal oxide layers (first metal oxide layer and second metal oxide layer) with distinct compositions and properties at different locations within the TFT structure. These layers have different oxygen vacancy concentrations and conductivity levels, enabling localized threshold voltage tuning in the channel region while maintaining overall device miniaturization

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent utilizes parameter changes by varying the metal oxide composition, oxygen content, and crystalline structure (amorphous vs. crystalline phases) of the metal oxide layers. By controlling oxygen plasma treatment conditions and metal oxide ratios, the threshold voltage can be adjusted across different device nodes without changing the overall device geometry

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple TFTs are integrated with MOSFETs in decreased feature sizes, then device performance improvement is desired, but the complexity of fabrication process increases

Engineering Contradiction:
Improvedevice performanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the formation of different metal oxide layers into a single sequential deposition process where the first metal oxide layer and second metal oxide layer are formed in succession. The implant mask is formed once to define both layers simultaneously, and a single oxygen plasma treatment step processes both layers, reducing the number of separate fabrication steps

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The implant mask serves multiple functions: it defines the pattern for both the first and second metal oxide layers, controls oxygen plasma exposure for both layers, and enables simultaneous threshold voltage tuning for multiple TFTs. This multi-functional approach simplifies the overall fabrication process while maintaining device performance

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the fabrication of TFTs with different threshold voltages, enhancing device performance and flexibility in logic circuit design by integrating BEOL metal oxide TFTs with FEOL CMOS transistors, improving conductivity and integration capabilities.

Implementation Method 1

performing an implantation operation on the first metal oxide layer and the second metal oxide layer

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Implementation Method 2

annealing processes

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS20240096706A1Semiconductor device including thin film transistor and method for forming the same
Publication Date: 2024.03.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240096706A1 patent drawing
  • US20240096706A1 patent drawing
  • US20240096706A1 patent drawing

AI summary

The present disclosure provides a method of forming a semiconductor device. The method includes: forming an interconnect structure over a substrate; forming a first gate structure and a second gate structure in a first layer of the interconnect structure; forming a first metal oxide layer and a second metal oxide layer in a second layer of the interconnect structure over the first gate structure and the second gate structure, respectively; forming an implant mask over the first metal oxide layer and the second metal oxide layer, the implant mask having different thicknesses corresponding to the first metal oxide layer and the second oxide layer; and performing an implantation operation on the first metal oxide layer and the second metal oxide layer.