Metal Oxide Source/Drain Electrodes for Low-Resistance Transistors
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Solution Overview
Problem
Current semiconductor integrated circuits (ICs) face challenges in scaling down transistor dimensions while maintaining effective source/drain electrode performance, leading to increased resistance and contact resistance issues due to the use of metallic materials, which affects device performance and manufacturing costs.
Innovation Solution
The use of highly doped metal oxide materials for source/drain electrodes, which have a higher electron concentration than the active layer, simplifies the fabrication process, reduces manufacturing costs, and improves interface quality with the active layer, minimizing Schottky barrier height and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metallic materials are used for source/drain electrodes, then electrical conductivity is improved, but contact resistance increases and manufacturing complexity increases due to fabrication challenges at scaled dimensions
Solution Approach 1:
The patent changes the material parameter from metallic to highly doped metal oxide, fundamentally altering the electrical and structural properties. This parameter change enables the formation of low-resistance contacts without the fabrication complexities associated with metallic materials at scaled dimensions, directly resolving the contradiction between reliability and device complexity
Solution Approach 2:
The patent employs composite material structures where highly doped metal oxide is combined with the semiconductor active layer. This composite approach achieves both low contact resistance and simplified fabrication, as the metal oxide can be deposited and doped in an integrated process flow that avoids the multiple steps required for metallic electrode fabrication
2Productivity
If transistor dimensions are scaled down, then functional density is improved, but resistance increases due to the use of metallic source/drain electrodes
Solution Approach 1:
By changing the material parameter to highly doped metal oxide with controlled electron concentration, the patent achieves low resistance even at scaled dimensions. The high doping level compensates for the reduced cross-sectional area, maintaining low resistance while enabling higher functional density
Solution Approach 2:
The patent applies local quality enhancement by creating a highly doped region specifically at the source/drain electrode interfaces with the active layer. This localized high electron concentration minimizes Schottky barrier height and contact resistance at the critical interface regions, while the overall transistor dimensions can be scaled down to increase functional density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for further scaling down of transistor dimensions, enhances device performance by reducing resistance, and maintains low contact resistance, thereby improving overall IC performance and efficiency.
Implementation Method 1
source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 1018 cm−3
Data Source
AI summary
A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 1018 cm−3. A semiconductor structure and a manufacturing method are also provided.


