Metal Oxide Transistor Etching to Prevent Parasitic Channels
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving stable and reliable electrical characteristics, particularly in the fabrication of transistors for display devices, due to issues with parasitic channels and reduced insulating layer thickness during the etching process.
Innovation Solution
A method involving the sequential formation of metal oxide films with varying crystallinity, where a higher crystallinity film is used as the semiconductor layer and a lower crystallinity film is used as the channel layer, with a conductive layer structure that includes copper or aluminum, and a specific etching process using resist masks to protect the source and drain electrodes during semiconductor film etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional etching process is used to form source and drain electrodes, then the etching process can be completed, but the insulating layer thickness is reduced and parasitic channels are formed
Solution Approach 1:
The source and drain electrodes are formed before the semiconductor film etching process. This preliminary action allows the electrodes to serve as part of the etching mask, protecting the insulating layer beneath them during subsequent etching operations, thereby preventing parasitic channel formation and maintaining insulating layer integrity
Solution Approach 2:
The fabrication process is divided into distinct sequential steps: first forming the conductive film for source and drain electrodes, then forming the semiconductor film, and finally performing etching. This segmentation allows each step to be optimized independently, ensuring electrode formation does not compromise insulating layer thickness
2Area of stationary object
If the insulating layer is made thinner to reduce device size, then the device area is reduced, but parasitic channels are formed and electrical characteristics become unstable
Solution Approach 1:
Source and drain electrodes are formed in advance before semiconductor film etching, creating a protective structure that prevents etching damage to the insulating layer. This allows the insulating layer to maintain sufficient thickness for electrical stability while the overall device area remains compact
Solution Approach 2:
The insulating layer thickness is maintained locally under the source and drain electrode regions through the protective etching process, while other areas of the device can be optimized for minimal area. This local quality differentiation allows simultaneous achievement of small device size and reliable electrical characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a transistor with improved electrical characteristics and high reliability by preventing parasitic channels and maintaining the integrity of the insulating layer, enabling better performance and productivity in display device fabrication.
Implementation Method 1
A metal oxide that can be used for a semiconductor layer can be formed by a sputtering method
Data Source
AI summary
A semiconductor device is fabricated by a method including the following steps: a first step of forming a semiconductor film containing a metal oxide over an insulating layer; a second step of forming a conductive film over the semiconductor film; a third step of forming a first resist mask over the conductive film and etching the conductive film to form a first conductive layer and to expose a top surface of the semiconductor film that is not covered with the first conductive layer; and a fourth step of forming a second resist mask that covers a top surface and a side surface of the first conductive layer and part of the top surface of the semiconductor film and etching the semiconductor film to form a semiconductor layer and to expose a top surface of the insulating layer that is not covered with the semiconductor layer.