Metal Pattern Density Uniformity in Inter-Layer Dielectrics
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Solution Overview
Problem
Achieving uniform pattern density of metal lines in inter-layer dielectrics is challenging, particularly in large chip areas without M0_PO patterns, leading to reduced device utilization and potential yield issues in etching and polishing processes.
Innovation Solution
A method involving the formation of intermediate metal features (M0_OD1 and M0_OD2) with specific etching and polishing steps to increase pattern density, including the use of CMP processes and damascene techniques to form M0_PO features with controlled widths and orientations, ensuring densities fall within the 1-20% range in 20 μm×20 μm chip areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy M0_PO patterns are inserted in large chip areas without metal patterns, then the pattern density increases and falls within the required range, but the device utilization rate decreases
Solution Approach 1:
The patent applies local quality by creating different metal pattern densities in different regions of the chip. Specifically, M0_OD2 features are formed only in first chip regions (such as diode and guard ring regions) that are adjacent to active devices, while leaving second chip regions with large areas without metal patterns unchanged. This localized approach increases pattern density where needed without wasting chip area with dummy patterns, thus resolving the contradiction between pattern density uniformity and device utilization rate.
2Productivity
If the pattern density is out of the specified range (1-20% in 20 μm×20 μm areas), then the chip area can be fully utilized for active devices, but the yield in etching and polishing processes is adversely affected
Solution Approach 1:
The patent applies preliminary action by forming M0_OD2 metal features in advance, before the final etching and polishing processes. These pre-formed metal features serve as a foundation that ensures the pattern density will be within the acceptable range during subsequent processing. By preparing the metal pattern structure beforehand in specific regions, the patent prevents yield issues in etching and polishing without requiring dummy patterns, thus maintaining both device utilization rate and process yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity and density of metal interconnect patterns, improving device utilization and yield by effectively distributing metal features across the chip, particularly in regions like diodes and guard rings, thus enhancing the performance of integrated circuits.
Implementation Method 1
polishing the metallic material to remove excess metallic materials
Data Source
AI summary
A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.