Sub-26 Nm Metal Feature Patterning With Conformal Spacer Deposition

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Solution Overview

Problem

Existing semiconductor manufacturing techniques face challenges in patterning and metallization of metal features with pitches less than 26 nm, leading to issues such as voids, seams, increased line resistance, and mechanical instability due to surface roughness and oxidation, particularly in advanced node interconnects.

Innovation Solution

A method involving conformal deposition of metal on spacers with a pitch twice the desired node pitch, followed by dielectric polishing and chemical-mechanical polishing to form solid metal features with reduced surface roughness and improved mechanical integrity, using techniques like ALD, CVD, and PVD.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional patterning and metallization techniques are used for metal features with pitches less than 26 nm, then manufacturing process simplicity is maintained, but surface roughness increases leading to increased line resistance and mechanical instability

Engineering Contradiction:
Improvesurface roughnessVSAvoidmetallization process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The metallization process is divided into multiple sequential deposition steps (barrier layer, metal layer, cap layer) with intermediate polishing operations. This segmentation allows each layer to be optimized independently for surface quality while managing overall process complexity through systematic breakdown of the metallization challenge.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A barrier layer is deposited prior to the metal layer to prevent oxidation and adhesion issues. This preliminary action addresses surface quality and mechanical stability concerns before the metal deposition occurs, preventing problems rather than correcting them afterward.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If conventional deposition methods are used for metal features with pitches less than 26 nm, then process simplicity is maintained, but voids and seams form in the metal features

Engineering Contradiction:
Improvemetal feature integrityVSAvoiddeposition process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The deposition process is segmented into multiple thin layers (barrier layer, metal layer, cap layer) deposited sequentially. This segmentation prevents void and seam formation by ensuring each thin layer deposits uniformly without gaps, while the combined structure achieves the required feature integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The deposition parameters are optimized for each individual layer with specific thickness controls (barrier layer 5-10 nm, metal layer 50-100 nm, cap layer 5-10 nm). By changing and controlling deposition parameters for each layer separately, uniform coverage is achieved without voids or seams.

Inventive Principle:
Principle #35Parameter changes

3Length of moving object

If metal features are patterned with sub-26 nm CDs, then advanced node interconnect requirements are met, but line resistance increases due to surface roughness

Engineering Contradiction:
Improvecritical dimensionVSAvoidsurface roughness
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The metal feature structure is segmented into multiple thin layers deposited sequentially. Each layer is deposited at controlled thicknesses (5-10 nm for barrier and cap layers, 50-100 nm for metal layer) to maintain smooth surfaces while achieving the required sub-26 nm critical dimensions, thereby reducing surface roughness-induced line resistance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Deposition parameters are precisely controlled and optimized for each layer to achieve smooth surfaces at sub-26 nm dimensions. The barrier layer thickness (5-10 nm), metal layer thickness (50-100 nm), and cap layer thickness (5-10 nm) are specifically tuned to minimize surface roughness while maintaining the required critical dimensions.

Inventive Principle:
Principle #35Parameter changes

4Manufacturing precision

If multi-layer conformal deposition is used to reduce surface roughness, then electrical performance improves, but process time and complexity increase

Engineering Contradiction:
Improvesurface roughnessVSAvoidprocess time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The metallization process is segmented into three conformal deposition steps (barrier layer, metal layer, cap layer) with intermediate polishing. While this segmentation improves surface roughness, the process time is managed by optimizing each deposition step's duration and utilizing parallel processing where possible.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The conformal deposition process maintains continuous useful action by depositing layers uniformly across the substrate without interruption. Each layer is deposited continuously to ensure uniform thickness and surface quality, maximizing the efficiency of each deposition step despite the multi-layer approach.

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the production of metal features with reduced surface roughness and improved electrical performance by reducing line resistance and mechanical stability, facilitating advanced node interconnects with sub-26 nm CDs and avoiding voids or seams.

Implementation Method 1

conformal deposition of metal on spacers with a pitch twice the desired node pitch

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

followed by dielectric polishing and chemical-mechanical polishing

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentEP4202989B1Patterning metal features on a substrate
Publication Date: 2026.01.07 INTEL CORP
  • EP4202989B1 patent drawingFigure 1
  • EP4202989B1 patent drawingFigure 2
  • EP4202989B1 patent drawingFigure 3A~3C

AI summary

Embodiments described herein may be related to apparatuses, processes, and techniques related to patterning and metallization to produce metal features on a substrate that have pitches less than 26 nm. Other embodiments may be described and/or claimed.