Self-Aligned Metal Plug Interconnects for Dense IC Fabrication
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Solution Overview
Problem
Existing methods for fabricating semiconductor integrated circuits face challenges in forming robust metal plug interconnections, particularly in scaling down processes where complex wiring and dielectric materials play a crucial role, leading to inefficiencies and increased manufacturing complexity.
Innovation Solution
A method involving the formation of hard masks and self-aligned metal plugs with multiple dielectric and barrier layers to ensure precise interconnects between conductive features, enhancing electrical isolation and process window relaxation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods are used for metal plug formation, then fabrication process is simpler, but interconnection robustness deteriorates
Solution Approach 1:
The fabrication process is divided into multiple stages: forming first and second conductive features at different depths, creating hard masks on specific features, depositing multiple dielectric layers with different properties, and forming metal plugs in a self-aligned manner. This segmentation allows each step to be optimized independently for robustness while maintaining overall process manageability
Solution Approach 2:
Hard masks are formed on conductive features before metal plug deposition, and multiple dielectric layers are deposited and patterned in advance. These preliminary actions establish precise alignment and protection structures that enable robust metal plug formation while reducing the complexity of subsequent steps through self-alignment
2Productivity
If scaling down process is applied, then production efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes vertical dimensionality by forming conductive features at different depths (first conductive feature with top surface above second conductive feature top surface) and depositing multiple dielectric layers at different levels. This three-dimensional approach enables higher device packing density and production efficiency while the self-aligned process maintains manufacturing feasibility
Solution Approach 2:
Multiple dielectric layers are nested around conductive features and metal plugs, with each layer serving specific functions (isolation, alignment, protection). This nested structure maximizes space utilization for higher density while organizing the complex manufacturing process into manageable concentric layers
3Reliability
If multiple dielectric and barrier layers are formed, then electrical isolation is improved, but process complexity increases
Solution Approach 1:
The hard masks formed on conductive features serve dual purposes: they provide electrical isolation through the dielectric layers and simultaneously serve as self-aligned masks for metal plug deposition. This self-service approach improves electrical isolation while reducing process complexity by eliminating separate alignment steps
Data Source
AI summary
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.