Low-Resistance Metal Plug Structure via Contact Sidewall Modification
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Solution Overview
Problem
Conventional FinFET device fabrication faces challenges with high contact resistance due to scaled-down critical dimensions and 3D profiles, leading to difficulties in metal plug resistance and interconnect resistance, which affects drive currents and increases fabrication costs.
Innovation Solution
A novel fabrication process involving ion implantation to modify the sidewalls of contact holes, forming a barrier layer with intensified structure to prevent inter-diffusion and enhance bottom-up metal deposition, reducing resistance and improving filling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contacts with barrier layers are used in FinFET devices, then device density and performance are improved, but contact resistance increases and metal filling becomes difficult
Solution Approach 1:
The patent changes the physical and chemical parameters of the contact hole sidewalls through ion implantation (modifying composition, density, and surface properties) to enable better metal deposition and reduce contact resistance while maintaining the necessary barrier functionality
Solution Approach 2:
The modified sidewall layer acts as an intermediary between the dielectric material and the metal plug, providing both barrier functionality and enhanced metal deposition properties, thus mediating between the conflicting requirements of barrier protection and low resistance
2Area of moving object
If contact hole dimensions are scaled down to increase device density, then higher device density is achieved, but contact resistance increases and metal filling capability deteriorates
Solution Approach 1:
The patent modifies the sidewall parameters (composition, density, surface energy) through ion implantation to improve wetting and deposition characteristics, enabling effective metal filling in scaled-down contact holes while maintaining high device density
Solution Approach 2:
The patent applies localized modification only to the contact hole sidewalls through targeted ion implantation, creating a region with enhanced properties for metal deposition without affecting the overall contact hole dimensions or the surrounding structure
3Ease of manufacture
If conventional deposition methods are used without sidewall modification, then fabrication process is simpler, but metal deposition quality and filling capability are poor
Solution Approach 1:
The patent performs preliminary ion implantation modification of the contact hole sidewalls before metal deposition, preparing the surface in advance to receive metal atoms more effectively, thus improving deposition quality without complicating the overall fabrication flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process achieves metal plugs with reduced resistance and enhanced filling capabilities, addressing the limitations of conventional FinFET devices by minimizing parasitic resistance and fabrication costs.
Implementation Method 1
performing an ion implantation process to sidewalls of the dielectric layer within the opening, thereby forming a barrier layer on the sidewalls
Implementation Method 2
performing a bottom-up deposition to fill the opening with a metal material, thereby forming a metal plug landing on the conductive feature
Data Source
AI summary
A semiconductor device that includes a semiconductor substrate, a dielectric layer over the semiconductor substrate, a conductive feature over the semiconductor substrate and buried in the dielectric layer, and a metal plug over the conductive feature and buried in the dielectric layer, where the dielectric layer has a hydrophobic sidewall facing the metal plug.